{"id":65053,"date":"2024-10-15T06:01:55","date_gmt":"2024-10-15T13:01:55","guid":{"rendered":"https:\/\/www.rambus.com\/?page_id=65053"},"modified":"2026-01-27T19:18:25","modified_gmt":"2026-01-28T03:18:25","slug":"ddr5-mrcd-and-mdb","status":"publish","type":"page","link":"https:\/\/www.rambus.com\/memory-interface-chips\/ddr5-dimm-chipset\/ddr5-mrcd-and-mdb\/","title":{"rendered":"DDR5 Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB)"},"content":{"rendered":"\t\t
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DDR5 Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB)<\/h1>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Delivering industry-leading memory bandwidth and capacity<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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The Rambus DDR5 Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB) enable industry-standard DDR5 Multiplexed Rank DIMMs (MRDIMMs) operating at data rates up to 12,800 MT\/s.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t

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Description<\/th>\nPart Number<\/th>\nProduct Brief<\/th>\nApplications<\/th>\n<\/tr>\n<\/thead>\n
12800 MT\/s Multiplexed Registering Clock Driver<\/td>\nD5MRCD2Gxx<\/td>\n\"Download<\/a><\/td>\nServer MRDIMM 12800<\/td>\n<\/tr>\n
12800 MT\/s Multiplexed Data Buffer<\/td>\nD5MDB2XGxx<\/td>\n\"Download<\/a><\/td>\nServer MRDIMM 12800<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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MRDIMM 12800 Showing MRCD and MDB (6 front, 4 back)<\/figcaption>\n\t\t\t\t\t\t\t\t\t\t<\/figure>\n\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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Each DDR5 MRDIMM 12800 requires one MRCD and ten MDB chips to multiplex the memory channel. The MRCD and MDB will also support a Tall MRDIMM form factor with four ranks of DDR5 DRAMs for double the capacity of a dual-rank RDIMM in a cost-effective manner.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Expanding Server Memory Capabilities with Multiplexed Rank DIMM (MRDIMM) Technology<\/h3>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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As per socket compute density increases, the amount of directly accessible, low-latency memory bandwidth and capacity to adequately feed data to the multiple cores needs to scale accordingly. Scaling memory bandwidth by increasing raw DRAM component bandwidth or by increasing the number of memory channels has challenges and is reaching limits. JEDEC has unveiled the development of a new DIMM technology called Multiplexed Rank Dual Inline Memory Modules (MRDIMM) to address the bandwidth challenge.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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From the blog<\/h3>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tMemory Bandwidth and DDR5 MRDIMMs Explained in this Ask the Experts\t\t\t<\/a>\n\t\t<\/h3>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tDDR5 vs DDR4 DRAM – All the Advantages & Design Challenges\t\t\t<\/a>\n\t\t<\/h3>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tJohn Eble Dives into Chipsets for Server and Client Systems in Ask the Experts\t\t\t<\/a>\n\t\t<\/h3>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/article>\n\t\t\t\t<\/div>\n\t\t\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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Data Center Evolution: DDR5 DIMMs Advance Server Performance<\/h3>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Driven by a confluence of megatrends, global data traffic is increasing at an exponential rate. For example, 5G networks are enabling billions of AI-powered IoT devices untethered from wired networks. Nowhere is the impact of all this growth being felt more intensely than in data centers. Indeed, hyperscale data centers have become the critical hubs of the global data network. DDR5 DRAM will enable the next generation of server systems providing the massive computing power of hyperscale and enterprise data centers. Learn about the benefits of DDR5 memory and the design considerations for implementing DDR5 DIMMs.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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\n\t\t\t\n\t\t\t\tRambus Delivers Industry-Leading Client Chipsets for Next-Generation AI PC Memory Modules\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tRambus Unveils Industry-First Complete Chipsets for Next-Generation DDR5 MRDIMMs and RDIMMs to Deliver Breakthrough Performance for Data Center and AI\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tRambus Expands Industry-Leading Memory Interface Chip Offering to High-Performance PCs with DDR5 Client Clock Driver\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t<\/div>\n\t\t\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tExpanding Server Memory Capabilities with MRDIMM Technology\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tCXL emerges as memory coherent fabric leader as GenZ Consortium transfers assets\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tCXL Memory Interconnect Initiative: Enabling a New Era of Data Center Architecture\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t<\/div>\n\t\t\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tHow AI is Shaping the Memory Market\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tMemory Interface Chip Solutions for PC Clients and AI\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tMemory Interface Chip Solutions for Servers and AI in the Data Center\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t<\/div>\n\t\t\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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\n\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\tContact Us<\/span>\n\t\t\t\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"

DDR5 Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB) Delivering industry-leading memory bandwidth and capacity Contact Us The Rambus DDR5 Multiplexed Registering Clock<\/p>\n","protected":false},"author":6,"featured_media":65054,"parent":20276,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"template-full.php","meta":{"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":"","_links_to":"","_links_to_target":""},"tags":[],"class_list":{"0":"post-65053","1":"page","2":"type-page","3":"status-publish","4":"has-post-thumbnail","6":"entry"},"yoast_head":"\nDDR5 Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB) | Memory Interface Chips - Rambus<\/title>\n<meta name=\"description\" content=\"The Rambus DDR5 Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB) enable industry-standard DDR5 Multiplexed Rank DIMMs (MRDIMMs) operating at data rates up to 12,800 MT\/s.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.rambus.com\/memory-interface-chips\/ddr5-dimm-chipset\/ddr5-mrcd-and-mdb\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"DDR5 Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB)\" \/>\n<meta property=\"og:description\" content=\"DDR5 Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB) Delivering industry-leading memory bandwidth and capacity Contact Us\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.rambus.com\/memory-interface-chips\/ddr5-dimm-chipset\/ddr5-mrcd-and-mdb\/\" \/>\n<meta property=\"og:site_name\" content=\"Rambus\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/RambusInc\" \/>\n<meta property=\"article:modified_time\" content=\"2026-01-28T03:18:25+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.rambus.com\/wp-content\/uploads\/2024\/10\/DDR5_MRDIMM2_Front_Side_with_Callouts_FB.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"1000\" \/>\n\t<meta property=\"og:image:height\" content=\"415\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:site\" content=\"@rambusinc\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.rambus.com\/memory-interface-chips\/ddr5-dimm-chipset\/ddr5-mrcd-and-mdb\/\",\"url\":\"https:\/\/www.rambus.com\/memory-interface-chips\/ddr5-dimm-chipset\/ddr5-mrcd-and-mdb\/\",\"name\":\"DDR5 Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB) | Memory Interface Chips - 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