{"id":64847,"date":"2024-09-09T14:00:29","date_gmt":"2024-09-09T21:00:29","guid":{"rendered":"https:\/\/www.rambus.com\/?p=64847"},"modified":"2024-10-08T10:03:16","modified_gmt":"2024-10-08T17:03:16","slug":"rambus-announces-industry-first-hbm4-controller-ip-to-accelerate-next-generation-ai-workloads","status":"publish","type":"post","link":"https:\/\/www.rambus.com\/rambus-announces-industry-first-hbm4-controller-ip-to-accelerate-next-generation-ai-workloads\/","title":{"rendered":"Rambus Announces Industry-First HBM4 Controller IP to Accelerate Next-Generation AI Workloads"},"content":{"rendered":"<p><strong>Highlights:<\/strong><\/p>\n<ul>\n<li><em>Built on a proven track record of over one hundred HBM design wins to ensure first-time silicon success<\/em><\/li>\n<li><em>Delivers more than double the throughput of HBM3 at low latency to meet the demands of Generative AI &amp; High-Performance Computing (HPC) workloads<\/em><\/li>\n<li><em>Expands industry-leading silicon IP portfolio of high-performance memory solutions<\/em><\/li>\n<\/ul>\n<p><img fetchpriority=\"high\" decoding=\"async\" class=\"size-full wp-image-64843\" src=\"https:\/\/www.rambus.com\/wp-content\/uploads\/2024\/09\/HBM4-Controller-Block-Diagram.png\" alt=\"HBM4 Controller Block Diagram\" width=\"1041\" height=\"604\" srcset=\"https:\/\/www.rambus.com\/wp-content\/uploads\/2024\/09\/HBM4-Controller-Block-Diagram.png 1041w, https:\/\/www.rambus.com\/wp-content\/uploads\/2024\/09\/HBM4-Controller-Block-Diagram-300x174.png 300w, https:\/\/www.rambus.com\/wp-content\/uploads\/2024\/09\/HBM4-Controller-Block-Diagram-1024x594.png 1024w, https:\/\/www.rambus.com\/wp-content\/uploads\/2024\/09\/HBM4-Controller-Block-Diagram-150x87.png 150w, https:\/\/www.rambus.com\/wp-content\/uploads\/2024\/09\/HBM4-Controller-Block-Diagram-768x446.png 768w\" sizes=\"(max-width: 1041px) 100vw, 1041px\" \/><\/p>\n<p>Figure 1: Rambus HBM4 Controller<\/p>\n<p><strong>SAN JOSE, Calif. \u2013 Sep. 9,<\/strong><strong> 2024 \u2013<\/strong> <a href=\"https:\/\/www.rambus.com\/\">Rambus Inc.<\/a> (NASDAQ:\u00a0<a href=\"https:\/\/finance.yahoo.com\/quote\/rmbs?ltr=1\">RMBS<\/a>), a premier chip and silicon IP provider making data faster and safer, today announced the industry\u2019s first <a href=\"https:\/\/www.rambus.com\/interface-ip\/hbm\/hbm4-controller\/\">HBM4 Memory Controller IP<\/a>, extending its market leadership in HBM IP with broad ecosystem support. This new solution supports the advanced feature set of HBM4 devices, and will enable designers to address the demanding memory bandwidth requirements of next-generation AI accelerators and graphics processing units (GPUs).<\/p>\n<p>\u201cWith Large Language Models (LLMs) now exceeding a trillion parameters and continuing to grow, overcoming bottlenecks in memory bandwidth and capacity is mission critical to meeting the real-time performance requirements of AI training and inference,\u201d said Neeraj Paliwal, SVP and general manager of Silicon IP, at Rambus.\u00a0\u201cAs the leading silicon IP provider for AI 2.0, we are bringing the industry\u2019s first HBM4 Controller IP solution to the market to help our customers unlock breakthrough performance in their state-of-the-art processors and accelerators.\u201d<\/p>\n<p>\u201cAs heterogeneous compute architectures are implemented at an ever-increasing scale to support a wide range of workloads with tremendous amounts of data movement, it is essential that the HBM IP ecosystem continues to extend performance and deliver interoperable solutions to meet the growing needs of customers,\u201d said Arif Khan, senior group director of protocol IP marketing in the Silicon Solutions Group at Cadence.\u00a0\u201cWe are pleased to see Rambus offer an interoperable HBM4 Controller IP solution to support the ecosystem alongside Cadence\u2019s leadership in HBM PHY and solutions performance once the industry transition to this new generation of HBM memory begins.\u201d<\/p>\n<p>\u201cHBM4 will represent a major advancement in memory technology for generative AI and other HPC applications,\u201d said Jongshin Shin, executive vice president and head of Foundry IP Ecosystem at Samsung Electronics. \u201cThe availability of HBM4 IP solutions will be critical to paving the path for widespread HBM4 adoption in the market and Samsung looks forward to collaborating closely with Rambus and the wider ecosystem to develop new HBM4 solutions for the AI era.\u201d<\/p>\n<p>\u201cIn today\u2019s complex and fast-paced semiconductor design landscape, pre-validated IP solutions are key to achieving first-time silicon success,\u201d said Abhi Kolpekwar, vice president and general manager, Digital Verification Technology division, Siemens Digital Industries Software. \u201cRambus and Siemens have a long-standing and successful collaboration to help our mutual customers meet their product and business goals, and we look forward to working together to deliver a new generation of best-in-class Rambus HBM4 memory controllers verified with Siemens\u2019 high-quality Verification IP.\u201d<\/p>\n<p>\u201cHBM is a key enabling technology for AI because AI processors and accelerators need high-performance, high-density memory for the massive computational requirements of AI workloads,&#8221; said Shane Rau, Research VP for Computing Semiconductors at IDC. &#8220;As AI processors and accelerators advance, they will need HBM to advance, too. Seeing HBM4 IP in the market now is a key enabling building block that will be ready for designers working on cutting-edge AI hardware.&#8221;<\/p>\n<p>The <a href=\"https:\/\/www.rambus.com\/interface-ip\/hbm\/\">Rambus HBM4 Controller<\/a> enables a new generation of HBM memory deployments for cutting-edge AI accelerators, graphics and HPC applications. The HBM4 Controller supports the JEDEC Spec of 6.4 Gigabits per second (Gbps). The Controller is further capable of supporting operation up to 10 Gbps providing a throughput of 2.56 Terabytes per second (TB\/s) to each memory device. The Rambus HBM4 Controller IP can be paired with third-party or customer PHY solutions to instantiate a complete HBM4 memory subsystem.<\/p>\n<p><strong>Availability and More Information<\/strong>:<\/p>\n<p>The Rambus HBM4 Controller IP is the latest addition to the Rambus leading-edge portfolio of digital controller solutions. The Controller is available for licensing, and early access design customers can engage today.<\/p>\n<p>Learn more about the Rambus HBM4 Controller IP at <a href=\"https:\/\/www.rambus.com\/interface-ip\/hbm\/\">https:\/\/www.rambus.com\/interface-ip\/hbm\/<\/a>.<\/p>\n<p><em>The HBM4 memory standard is in development by JEDEC. JEDEC standards are subject to change during and after the development process, including disapproval by the JEDEC Board of Directors.<\/em><\/p>\n<p><strong>Forward-looking statements<\/strong><\/p>\n<p>Information set forth in this press release, including statements as to Rambus\u2019 outlook and financial estimates and statements as to the expected timing and effects of Rambus products, constitute forward-looking statements within the meaning of the safe harbor provisions of the Private Securities Litigation Reform Act of 1995.<\/p>\n<p>These statements are based on various assumptions and the current expectations of the management of Rambus and may not be accurate because of risks and uncertainties surrounding these assumptions and expectations. Factors listed below, as well as other factors, may cause actual results to differ significantly from these forward-looking statements. There is no guarantee that any of the events anticipated by these forward-looking statements will occur, or what effect they will have on the operations or financial condition of Rambus. Forward-looking statements included herein are made as of the date hereof, and Rambus undertakes no obligation to publicly update or revise any forward-looking statement unless required to do so by federal securities laws.<\/p>\n<p>Major risks, uncertainties and assumptions include, but are not limited to: any statements regarding anticipated operational and financial results; any statements of expectation or belief; other factors described under &#8220;Risk Factors&#8221; in Rambus\u2019 Annual Report on Form 10-K and Quarterly Reports on Form 10-Q; and any statements of assumptions underlying any of the foregoing. It is not possible to predict or identify all such factors. Consequently, while the list of factors presented here is considered representative, no such list should be considered to be a complete statement of all potential risks and uncertainties.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Highlights: Built on a proven track record of over one hundred HBM design wins to ensure first-time silicon success Delivers more than double the throughput of HBM3 at low latency to meet the demands of Generative AI &amp; High-Performance Computing (HPC) workloads Expands industry-leading silicon IP portfolio of high-performance memory solutions Figure 1: Rambus HBM4 [&hellip;]<\/p>\n","protected":false},"author":6,"featured_media":64848,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":"","_links_to":"","_links_to_target":""},"categories":[26089,475,34],"tags":[],"class_list":{"0":"post-64847","1":"post","2":"type-post","3":"status-publish","4":"format-standard","5":"has-post-thumbnail","7":"category-press-releases-controllers","8":"category-memory-interface","9":"category-pressreleases","10":"entry"},"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.9 (Yoast SEO v26.9) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Rambus Announces Industry-First HBM4 Controller IP to Accelerate Next-Generation AI Workloads - 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