{"id":61165,"date":"2021-12-13T19:25:39","date_gmt":"2021-12-14T03:25:39","guid":{"rendered":"https:\/\/www.rambus.com\/?p=61165"},"modified":"2024-03-27T13:50:06","modified_gmt":"2024-03-27T20:50:06","slug":"demonstration-of-a-cxl-interconnect-on-a-fpga-based-design","status":"publish","type":"post","link":"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/","title":{"rendered":"Demonstration of a CXL Interconnect on a FPGA-based design"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"61165\" class=\"elementor elementor-61165\" data-elementor-post-type=\"post\">\n\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-3e2d517c elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"3e2d517c\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-47697240\" data-id=\"47697240\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<section class=\"elementor-section elementor-inner-section elementor-element elementor-element-2023bb40 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"2023bb40\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-66 elementor-inner-column elementor-element elementor-element-275823c9\" data-id=\"275823c9\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-1e31f519 elementor-widget elementor-widget-text-editor\" data-id=\"1e31f519\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>In this video, we demonstrate the Rambus Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory, or HDM. This demonstration is performed using Intel\u2019s Pre-Production Xeon processor as a host, connected to an FPGA board, instantiating Rambus&#8217; CXL Controller and CXL.mem test design.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<div class=\"elementor-column elementor-col-33 elementor-inner-column elementor-element elementor-element-2fccee5\" data-id=\"2fccee5\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-722e0a10 elementor-widget elementor-widget-video\" data-id=\"722e0a10\" data-element_type=\"widget\" data-e-type=\"widget\" data-settings=\"{&quot;youtube_url&quot;:&quot;https:\\\/\\\/youtu.be\\\/NPHU1tcc4hQ&quot;,&quot;video_type&quot;:&quot;youtube&quot;,&quot;controls&quot;:&quot;yes&quot;}\" data-widget_type=\"video.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-wrapper elementor-open-inline\">\n\t\t\t<div class=\"elementor-video\"><\/div>\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>In this video, we demonstrate the Rambus Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory, or HDM. This demonstration is performed using Intel\u2019s Pre-Production Xeon processor as a host, connected to an FPGA board, instantiating Rambus&#8217; CXL Controller and CXL.mem test design.<\/p>\n","protected":false},"author":6,"featured_media":61161,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":"","_links_to":"","_links_to_target":""},"categories":[26056,510,4],"tags":[],"class_list":{"0":"post-61165","1":"post","2":"type-post","3":"status-publish","4":"format-standard","5":"has-post-thumbnail","7":"category-controllers","8":"category-memory-interface-videos","9":"category-videos","10":"business_unit-controllers","11":"business_unit-cxl-controllers","12":"resource_type-videos","13":"entry"},"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.9 (Yoast SEO v26.9) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Demonstration of a CXL Interconnect on a FPGA-based design - Rambus<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Demonstration of a CXL Interconnect on a FPGA-based design\" \/>\n<meta property=\"og:description\" content=\"In this video, we demonstrate the Rambus Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory, or HDM. This\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/\" \/>\n<meta property=\"og:site_name\" content=\"Rambus\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/RambusInc\" \/>\n<meta property=\"article:published_time\" content=\"2021-12-14T03:25:39+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2024-03-27T20:50:06+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.rambus.com\/wp-content\/uploads\/2022\/01\/cxl-demo-video.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"500\" \/>\n\t<meta property=\"og:image:height\" content=\"286\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"fongj@rambus.com\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@rambusinc\" \/>\n<meta name=\"twitter:site\" content=\"@rambusinc\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#article\",\"isPartOf\":{\"@id\":\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/\"},\"author\":{\"name\":\"fongj@rambus.com\",\"@id\":\"https:\/\/www.rambus.com\/#\/schema\/person\/37e2e7e0a04304c805d567b056b6282e\"},\"headline\":\"Demonstration of a CXL Interconnect on a FPGA-based design\",\"datePublished\":\"2021-12-14T03:25:39+00:00\",\"dateModified\":\"2024-03-27T20:50:06+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/\"},\"wordCount\":66,\"commentCount\":0,\"publisher\":{\"@id\":\"https:\/\/www.rambus.com\/#organization\"},\"image\":{\"@id\":\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#primaryimage\"},\"thumbnailUrl\":\"https:\/\/www.rambus.com\/wp-content\/uploads\/2022\/01\/cxl-demo-video.jpg\",\"articleSection\":[\"Controllers\",\"Interface IP\",\"Videos\"],\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"CommentAction\",\"name\":\"Comment\",\"target\":[\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#respond\"]}]},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/\",\"url\":\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/\",\"name\":\"Demonstration of a CXL Interconnect on a FPGA-based design - Rambus\",\"isPartOf\":{\"@id\":\"https:\/\/www.rambus.com\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#primaryimage\"},\"image\":{\"@id\":\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#primaryimage\"},\"thumbnailUrl\":\"https:\/\/www.rambus.com\/wp-content\/uploads\/2022\/01\/cxl-demo-video.jpg\",\"datePublished\":\"2021-12-14T03:25:39+00:00\",\"dateModified\":\"2024-03-27T20:50:06+00:00\",\"breadcrumb\":{\"@id\":\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#primaryimage\",\"url\":\"https:\/\/www.rambus.com\/wp-content\/uploads\/2022\/01\/cxl-demo-video.jpg\",\"contentUrl\":\"https:\/\/www.rambus.com\/wp-content\/uploads\/2022\/01\/cxl-demo-video.jpg\",\"width\":500,\"height\":286,\"caption\":\"Watch a video demonstrate of our Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory.\"},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/www.rambus.com\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Videos\",\"item\":\"https:\/\/www.rambus.com\/videos\/\"},{\"@type\":\"ListItem\",\"position\":3,\"name\":\"Demonstration of a CXL Interconnect on a FPGA-based design\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.rambus.com\/#website\",\"url\":\"https:\/\/www.rambus.com\/\",\"name\":\"Rambus\",\"description\":\"At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.\",\"publisher\":{\"@id\":\"https:\/\/www.rambus.com\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.rambus.com\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-US\"},{\"@type\":\"Organization\",\"@id\":\"https:\/\/www.rambus.com\/#organization\",\"name\":\"Rambus\",\"url\":\"https:\/\/www.rambus.com\/\",\"logo\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/www.rambus.com\/#\/schema\/logo\/image\/\",\"url\":\"https:\/\/www.rambus.com\/wp-content\/uploads\/2025\/09\/Rambus_Logo.png\",\"contentUrl\":\"https:\/\/www.rambus.com\/wp-content\/uploads\/2025\/09\/Rambus_Logo.png\",\"width\":200,\"height\":62,\"caption\":\"Rambus\"},\"image\":{\"@id\":\"https:\/\/www.rambus.com\/#\/schema\/logo\/image\/\"},\"sameAs\":[\"https:\/\/www.facebook.com\/RambusInc\",\"https:\/\/x.com\/rambusinc\",\"https:\/\/www.linkedin.com\/company\/rambus\",\"https:\/\/www.youtube.com\/user\/RambusWeb\"],\"description\":\"Rambus is a provider of industry-leading chips and silicon IP.\",\"email\":\"ebiz@rambus.com\",\"telephone\":\"+1-408-462-8000\",\"legalName\":\"Rambus Inc.\",\"numberOfEmployees\":{\"@type\":\"QuantitativeValue\",\"minValue\":\"501\",\"maxValue\":\"1000\"}},{\"@type\":\"Person\",\"@id\":\"https:\/\/www.rambus.com\/#\/schema\/person\/37e2e7e0a04304c805d567b056b6282e\",\"name\":\"fongj@rambus.com\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/www.rambus.com\/#\/schema\/person\/image\/\",\"url\":\"https:\/\/secure.gravatar.com\/avatar\/eef6b189dc8119b048e438b0632a5939d30dd389395900b997b809f52cb059db?s=96&d=blank&r=g\",\"contentUrl\":\"https:\/\/secure.gravatar.com\/avatar\/eef6b189dc8119b048e438b0632a5939d30dd389395900b997b809f52cb059db?s=96&d=blank&r=g\",\"caption\":\"fongj@rambus.com\"},\"url\":\"https:\/\/www.rambus.com\/author\/fongjrambus-com\/\"}]}<\/script>\n<!-- \/ Yoast SEO Premium plugin. -->","yoast_head_json":{"title":"Demonstration of a CXL Interconnect on a FPGA-based design - Rambus","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/","og_locale":"en_US","og_type":"article","og_title":"Demonstration of a CXL Interconnect on a FPGA-based design","og_description":"In this video, we demonstrate the Rambus Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory, or HDM. This","og_url":"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/","og_site_name":"Rambus","article_publisher":"https:\/\/www.facebook.com\/RambusInc","article_published_time":"2021-12-14T03:25:39+00:00","article_modified_time":"2024-03-27T20:50:06+00:00","og_image":[{"width":500,"height":286,"url":"https:\/\/www.rambus.com\/wp-content\/uploads\/2022\/01\/cxl-demo-video.jpg","type":"image\/jpeg"}],"author":"fongj@rambus.com","twitter_card":"summary_large_image","twitter_creator":"@rambusinc","twitter_site":"@rambusinc","schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#article","isPartOf":{"@id":"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/"},"author":{"name":"fongj@rambus.com","@id":"https:\/\/www.rambus.com\/#\/schema\/person\/37e2e7e0a04304c805d567b056b6282e"},"headline":"Demonstration of a CXL Interconnect on a FPGA-based design","datePublished":"2021-12-14T03:25:39+00:00","dateModified":"2024-03-27T20:50:06+00:00","mainEntityOfPage":{"@id":"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/"},"wordCount":66,"commentCount":0,"publisher":{"@id":"https:\/\/www.rambus.com\/#organization"},"image":{"@id":"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#primaryimage"},"thumbnailUrl":"https:\/\/www.rambus.com\/wp-content\/uploads\/2022\/01\/cxl-demo-video.jpg","articleSection":["Controllers","Interface IP","Videos"],"inLanguage":"en-US","potentialAction":[{"@type":"CommentAction","name":"Comment","target":["https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#respond"]}]},{"@type":"WebPage","@id":"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/","url":"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/","name":"Demonstration of a CXL Interconnect on a FPGA-based design - Rambus","isPartOf":{"@id":"https:\/\/www.rambus.com\/#website"},"primaryImageOfPage":{"@id":"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#primaryimage"},"image":{"@id":"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#primaryimage"},"thumbnailUrl":"https:\/\/www.rambus.com\/wp-content\/uploads\/2022\/01\/cxl-demo-video.jpg","datePublished":"2021-12-14T03:25:39+00:00","dateModified":"2024-03-27T20:50:06+00:00","breadcrumb":{"@id":"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/"]}]},{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#primaryimage","url":"https:\/\/www.rambus.com\/wp-content\/uploads\/2022\/01\/cxl-demo-video.jpg","contentUrl":"https:\/\/www.rambus.com\/wp-content\/uploads\/2022\/01\/cxl-demo-video.jpg","width":500,"height":286,"caption":"Watch a video demonstrate of our Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory."},{"@type":"BreadcrumbList","@id":"https:\/\/www.rambus.com\/demonstration-of-a-cxl-interconnect-on-a-fpga-based-design\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/www.rambus.com\/"},{"@type":"ListItem","position":2,"name":"Videos","item":"https:\/\/www.rambus.com\/videos\/"},{"@type":"ListItem","position":3,"name":"Demonstration of a CXL Interconnect on a FPGA-based design"}]},{"@type":"WebSite","@id":"https:\/\/www.rambus.com\/#website","url":"https:\/\/www.rambus.com\/","name":"Rambus","description":"At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.","publisher":{"@id":"https:\/\/www.rambus.com\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.rambus.com\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-US"},{"@type":"Organization","@id":"https:\/\/www.rambus.com\/#organization","name":"Rambus","url":"https:\/\/www.rambus.com\/","logo":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/www.rambus.com\/#\/schema\/logo\/image\/","url":"https:\/\/www.rambus.com\/wp-content\/uploads\/2025\/09\/Rambus_Logo.png","contentUrl":"https:\/\/www.rambus.com\/wp-content\/uploads\/2025\/09\/Rambus_Logo.png","width":200,"height":62,"caption":"Rambus"},"image":{"@id":"https:\/\/www.rambus.com\/#\/schema\/logo\/image\/"},"sameAs":["https:\/\/www.facebook.com\/RambusInc","https:\/\/x.com\/rambusinc","https:\/\/www.linkedin.com\/company\/rambus","https:\/\/www.youtube.com\/user\/RambusWeb"],"description":"Rambus is a provider of industry-leading chips and silicon IP.","email":"ebiz@rambus.com","telephone":"+1-408-462-8000","legalName":"Rambus Inc.","numberOfEmployees":{"@type":"QuantitativeValue","minValue":"501","maxValue":"1000"}},{"@type":"Person","@id":"https:\/\/www.rambus.com\/#\/schema\/person\/37e2e7e0a04304c805d567b056b6282e","name":"fongj@rambus.com","image":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/www.rambus.com\/#\/schema\/person\/image\/","url":"https:\/\/secure.gravatar.com\/avatar\/eef6b189dc8119b048e438b0632a5939d30dd389395900b997b809f52cb059db?s=96&d=blank&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/eef6b189dc8119b048e438b0632a5939d30dd389395900b997b809f52cb059db?s=96&d=blank&r=g","caption":"fongj@rambus.com"},"url":"https:\/\/www.rambus.com\/author\/fongjrambus-com\/"}]}},"_links":{"self":[{"href":"https:\/\/www.rambus.com\/wp-json\/wp\/v2\/posts\/61165","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.rambus.com\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.rambus.com\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.rambus.com\/wp-json\/wp\/v2\/users\/6"}],"replies":[{"embeddable":true,"href":"https:\/\/www.rambus.com\/wp-json\/wp\/v2\/comments?post=61165"}],"version-history":[{"count":0,"href":"https:\/\/www.rambus.com\/wp-json\/wp\/v2\/posts\/61165\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.rambus.com\/wp-json\/wp\/v2\/media\/61161"}],"wp:attachment":[{"href":"https:\/\/www.rambus.com\/wp-json\/wp\/v2\/media?parent=61165"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.rambus.com\/wp-json\/wp\/v2\/categories?post=61165"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.rambus.com\/wp-json\/wp\/v2\/tags?post=61165"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}