{"id":60608,"date":"2021-08-18T06:02:10","date_gmt":"2021-08-18T13:02:10","guid":{"rendered":"https:\/\/www.rambus.com\/?page_id=60608"},"modified":"2024-03-21T11:32:54","modified_gmt":"2024-03-21T18:32:54","slug":"debug-and-test-solutions","status":"publish","type":"page","link":"https:\/\/www.rambus.com\/interface-ip\/pci-express\/debug-and-test-solutions\/","title":{"rendered":"Debug and Test Solutions"},"content":{"rendered":"\t\t
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Debug and Test Solutions<\/h1>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Home<\/a><\/span><\/span><\/p>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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INSPECTOR for PCIe 5.0<\/h2>

Interposer Card for Diagnostic Testing, Exercising and Debug of PCIe Devices at up to Gen5 32 GT\/s speed.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t

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INSPECTOR is a PCIe 5.0-compliant interposer module designed for non-intrusive\u00a0monitoring, diagnostic, exercising and debug of PCIe devices. INSPECTOR uses transparent switching technology to connect on the upstream side to a PCIe\u00a0host platform, and on the downstream side to the device under test (DUT). INSPECTOR supports PCIe 1.x, 2.x, 3.x, 4.x and 5.0 interfaces on either ports<\/span>, and up to 4 lanes (x4) at maximum data rate. It is typically used for bring-up and diagnostic testing of PCIe 5.0 DUTs at PCIe 5.0 32 GT\/s speed using existing PCIe hosts operating at PCIe 4.0 16 GT\/s speed, but can support any link speed\/width combination on upstream and downstream ports. INSPECTOR\u2019s built-in diagnostic capabilities allow validation engineers to instantly diagnose issues with their PCIe devices, without the need for expensive test equipment.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t

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Watch this video and learn how to test and debug PCIe 5.0 devices with Inspector<\/em><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Gen5HOST<\/h2>

PCIe 5.0 Host Enabling Reference Platform for Prototyping & Development of PCIe 5.0 Devices and Applications.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t

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Gen5HOST<\/figcaption>\n\t\t\t\t\t\t\t\t\t\t<\/figure>\n\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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Gen5HOST provides a platform for prototyping and developing PCIe 5.0 hardware and software. At the core of Gen5HOST is the Rambus PCIe 5.0 Switch IP running on a Xilinx\u00ae Virtex\u00ae UltraScale+\u2122 FPGA. Gen5HOST provides a PCIe 4.0 x8 (upstream) to PCIe 5.0 x4 (downstream) integration backplane for development and validation of PCIe 5.0 endpoints, and is also available in a reversed configuration (PCIe 5.0 upstream, PCIe 4.0 downstream) for development and validation of PCIe 5.0 Hosts and Root Complexes. By working with Gen5HOST, developers of PCIe 5.0 devices can accelerate their software, firmware, and hardware developments, in their production environment, using the operating system of their choosing.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Gen5ENDPOINT<\/h2>

PCIe 5.0 Endpoint Reference Platform for Prototyping and Development of PCIe 5.0 Root Port\/Host Silicon and Devices.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t

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Gen5ENDPOINT<\/figcaption>\n\t\t\t\t\t\t\t\t\t\t<\/figure>\n\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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Gen5ENDPOINT is a PCIe add-in card suitable for prototyping and developing PCIe 5.0 hardware and software. At the core of Gen5ENDPOINT is the Rambus PCIe 5.0 Switch IP running on a Xilinx\u00ae Virtex\u00ae UltraScale+\u2122 FPGA. Gen5ENDPOINT features an integrated PCIe 5.0 endpoint agent with DMA and memory-mapped I\/O capability. By working with Gen5ENDPOINT, developers of PCIe 5.0 host systems and root complexes can accelerate their software, firmware, and hardware developments, in their production environment, using the operating system of their choosing.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Data Center Evolution: The Leap to 64 GT\/s Signaling with PCI Express 6.1<\/h3>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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The PCI Express\u00ae (PCIe\u00ae) interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the rapid rise in bandwidth demands of advanced workloads such as AI\/ML training, PCIe 6.1\u00a0jumps signaling to 64 GT\/s with some of the biggest changes yet in the standard.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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From the blog<\/h2><\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tPowering the Next Wave of AI Inference with the Rambus GDDR6 PHY at 24 Gb\/s\t\t\t<\/a>\n\t\t<\/h3>\n\t\t\n\t\t\n\t\t\tRead More \u00bb\t\t<\/a>\n\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tAccelerating AI\/ML applications in the data center with HBM3\t\t\t<\/a>\n\t\t<\/h3>\n\t\t\n\t\t\n\t\t\tRead More \u00bb\t\t<\/a>\n\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tRambus Design Summit Interview Series: Steven Woo\t\t\t<\/a>\n\t\t<\/h3>\n\t\t\n\t\t\n\t\t\tRead More \u00bb\t\t<\/a>\n\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/article>\n\t\t\t\t<\/div>\n\t\t\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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Resources<\/span><\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tRambus Advances AI\/ML Performance with 8.4 Gbps HBM3-Ready Memory Subsystem\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tRambus Expands High-Performance Memory Subsystem Offerings with HBM2E Solution on Samsung 14\/11nm\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tRambus Advances HBM2E Performance to 4.0 Gbps for AI\/ML Training Applications\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t<\/div>\n\t\t\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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Related Papers<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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\n\t\t\t\n\t\t\t\tMIPI DSI-2 & VESA Video Compression Drive Performance for Next-Generation Displays\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tSupercharging AI Inference with GDDR7\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t<\/div>\n\t\t\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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Testing and debugging PCIe 5.0 devices with Inspector\n<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Related Markets & Applications<\/span><\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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\n\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\tAI & Machine Learning<\/span>\n\t\t\t\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\tEdge<\/span>\n\t\t\t\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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