{"id":60369,"date":"2021-06-16T06:04:15","date_gmt":"2021-06-16T13:04:15","guid":{"rendered":"https:\/\/www.rambus.com\/?page_id=60369"},"modified":"2026-01-27T19:35:37","modified_gmt":"2026-01-28T03:35:37","slug":"cxl-memory-initiative","status":"publish","type":"page","link":"https:\/\/www.rambus.com\/cxl-memory-initiative\/","title":{"rendered":"CXL Memory Initiative"},"content":{"rendered":"\t\t
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CXL Memory Initiative <\/h1>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\t\t\t\t\t\tEnabling new memory tiers for breakthrough server performance\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Home<\/a><\/span><\/span><\/p>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Data Center Challenges<\/h2>

Data centers face three major memory challenges as roadblocks to greater performance and total cost of ownership (TCO).<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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The first of these is the limitations of the current server memory hierarchy. There is a three order of magnitude latency gap that exists between direct-attached DRAM and Solid-State Drive (SSD) storage. When a processor runs out of capacity in direct-attached memory, it must go to SSD, which leaves the processor waiting. That waiting, or latency, has a dramatic negative impact on computing performance.<\/p>

Secondly, core counts in multi-core processors are scaling far faster than main memory channels. This translates to processor cores beyond a certain number being starved for memory bandwidth, sub-optimizing the benefit of additional cores.<\/p>

Finally, with the increasing move to accelerated computing, wherein accelerators have their own directed attached memory, there is the growing problem of underutilized or stranded memory resources.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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How CXL Technology will Revolutionize the Data Center<\/h3>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\t\t\t\t\t\tWith CXL technology, the industry is pursuing tiered-memory solutions and composable architectures that would match the amount of compute, memory and storage in an on-demand fashion to address the needs of a wide range of workloads. Learn how over 200 companies, including the leaders at every level of the data center value chain from IP, chips, platforms, system OEMs to hyperscalers, are coalescing to revolutionize the data center. \t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Meeting the Challenges with CXL<\/h2>

The solution to the data center memory challenges is a complimentary, pin-efficient memory technology that can provide more bandwidth and capacity to processors in a flexible manner. Compute Express Link\u2122 (CXL\u2122) is the broadly supported industry standard solution that has been developed to provide low-latency, memory cache coherent links between processors, accelerators and memory devices.<\/p>

CXL leverages PCI Express\u00ae, which is ubiquitous in data centers, for its physical layer. With CXL, new memory tiers can be implemented which bridge the gap between direct-attached memory and SSD to unlock the power of multi-core processors.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t

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In addition, CXL\u2019s memory cache coherency allows memory resources to be shared between processors and accelerators. Sharing of memory is the key to tackling that stranded memory resource problem.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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CXL Memory Expansion and Pooling<\/h3>

CXL enables a number of use models which deliver increasing levels of bandwidth and capacity for a tradeoff in latency. The first of these use models, or memory tiers, shown on the right in the figure below is memory expansion which provides increased bandwidth and capacity at a latency approaching that of direct-attached memory.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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CXL Memory Tiers and Benefits <\/figcaption>\n\t\t\t\t\t\t\t\t\t\t<\/figure>\n\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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CXL memory pooling allows for multiple compute nodes (processors and accelerators) to access multiple CXL memory devices in an on-demand fashion providing flexible and efficient access to greater memory bandwidth and capacity. This same concept can be scaled out through CXL switching and fabrics.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Rambus CXL Memory Initiative<\/h3>

Through the CXL Memory Initiative, Rambus is developing solutions to enable a new era of data center performance and efficiency. This initiative is the latest chapter in the 30-year history of Rambus leadership in state-of-the-art memory and chip-to-chip interconnect products.<\/p>

Chip solutions needed for CXL memory expansion and pooling require the synthesis of a number of critical technologies. Rambus expertise in memory and SerDes subsystems, semiconductor and network security, high-volume memory interface chips and compute system architectures will make possible the breakthrough CXL memory solutions for the future data center.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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CXL Memory Interconnect Initiative: Enabling a New Era of Data Center Architecture<\/h3>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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In response to an exponential growth in data, the industry is on the threshold of a groundbreaking architectural shift that will fundamentally change the performance, efficiency and cost of data centers around the globe. Server architecture, which has remained largely unchanged for decades, is taking a revolutionary step forward to address the growing demand for data and the voracious performance requirements of advanced workloads.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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\n\t\t\t\n\t\t\t\tRambus CXL IP: A Journey from Spec to Compliance\t\t\t<\/a>\n\t\t<\/h3>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tRambus, VIAVI and Samtec Demonstrate CXL\u00ae over Optics PoC at Upcoming SC24\t\t\t<\/a>\n\t\t<\/h3>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tRambus CXL IP Advances Data Center Capabilities in CXL Over Optics Demo\t\t\t<\/a>\n\t\t<\/h3>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/article>\n\t\t\t\t<\/div>\n\t\t\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tRambus Announces Industry-First HBM4 Controller IP to Accelerate Next-Generation AI Workloads\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tRambus Boosts AI Performance with 9.6 Gbps HBM3 Memory Controller IP\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tSupercharging AI Inference with GDDR7\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t<\/div>\n\t\t\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tSupercharging AI Inference with GDDR7\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t<\/div>\n\t\t\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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CXL Memory Initiative Enabling new memory tiers for breakthrough server performance Contact Us Data Center Challenges Data centers face three major memory challenges as roadblocks<\/p>\n","protected":false},"author":6,"featured_media":60408,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"template-full.php","meta":{"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":"","_links_to":"","_links_to_target":""},"tags":[],"class_list":{"0":"post-60369","1":"page","2":"type-page","3":"status-publish","4":"has-post-thumbnail","6":"entry"},"yoast_head":"\nCXL Memory Initiative - Rambus<\/title>\n<meta name=\"description\" content=\"Through the CXL Memory Initiative, Rambus is developing solutions to enable a new era of data center performance and efficiency.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.rambus.com\/cxl-memory-initiative\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"CXL Memory Initiative\" \/>\n<meta property=\"og:description\" content=\"CXL Memory Initiative Enabling new memory tiers for breakthrough server performance Contact Us Data Center ChallengesData centers face three major memory\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.rambus.com\/cxl-memory-initiative\/\" \/>\n<meta property=\"og:site_name\" content=\"Rambus\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/RambusInc\" \/>\n<meta property=\"article:modified_time\" content=\"2026-01-28T03:35:37+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.rambus.com\/wp-content\/uploads\/2021\/06\/cxl-in-data-center.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"500\" \/>\n\t<meta property=\"og:image:height\" content=\"286\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:site\" content=\"@rambusinc\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.rambus.com\/cxl-memory-initiative\/\",\"url\":\"https:\/\/www.rambus.com\/cxl-memory-initiative\/\",\"name\":\"CXL Memory Initiative - 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