{"id":60209,"date":"2021-04-21T14:01:08","date_gmt":"2021-04-21T21:01:08","guid":{"rendered":"https:\/\/www.rambus.com\/?p=60209"},"modified":"2021-04-21T14:01:08","modified_gmt":"2021-04-21T21:01:08","slug":"rambus-expands-high-performance-memory-subsystem-offerings-with-hbm2e-solution-on-samsung-14-11nm","status":"publish","type":"post","link":"https:\/\/www.rambus.com\/rambus-expands-high-performance-memory-subsystem-offerings-with-hbm2e-solution-on-samsung-14-11nm\/","title":{"rendered":"Rambus Expands High-Performance Memory Subsystem Offerings with HBM2E Solution on Samsung 14\/11nm"},"content":{"rendered":"<p><strong>Highlights:\u00a0<\/strong><\/p>\n<ul>\n<li><em>Supports\u00a0accelerators requiring terabyte-scale bandwidth for artificial intelligence\/machine learning (AI\/ML) training applications <\/em><\/li>\n<li><em>Fully-integrated HBM2E memory interface subsystem, consisting of verified PHY and controller, silicon proven on advanced Samsung 14\/11nm FinFET process<\/em><\/li>\n<li><em>Backed by unrivaled system expertise supporting customers with interposer and package reference designs to speed time to market<\/em><\/li>\n<\/ul>\n<p><strong>SAN JOSE, Calif. \u2013\u00a0April 21, 2021\u00a0<\/strong>\u2013\u00a0<a href=\"https:\/\/www.rambus.com\/\">Rambus Inc.<\/a>\u00a0(NASDAQ:\u00a0<a href=\"https:\/\/finance.yahoo.com\/quote\/rmbs?ltr=1\">RMBS<\/a>), a provider of industry-leading chips and silicon IP making data faster and safer, today announced the\u00a0<a href=\"https:\/\/www.rambus.com\/interface-ip\/ddrn-phys\/hbm\/\">Rambus\u00a0HBM2E memory interface subsystem<\/a><u>,<\/u>\u00a0consisting of a fully-integrated PHY and controller, is silicon proven on Samsung\u2019s advanced 14\/11nm FinFET process. Leveraging over 30 years of signal integrity expertise, the Rambus solution operates up to 3.2 Gbps, delivering 410 GB\/s of bandwidth. This performance meets the terabyte-scale bandwidth needs of accelerators targeting the most demanding AI\/ML training and high-performance computing (HPC) applications.<\/p>\n<p>\u201cOur partnership with Rambus brings together industry-leading memory interface design expertise with Samsung\u2019s state-of-the-art process and packaging technologies,\u201d said Jongshin Shin, vice president of Design Platform Development at Samsung Electronics. \u201cDesigners of AI and HPC systems can implement platforms using HBM2E memory leveraging Samsung\u2019s advanced 14\/11nm process to achieve unmatched levels of performance.\u201d<\/p>\n<p>The fully-integrated, production-ready Rambus HBM2E memory subsystem runs at 3.2 Gbps and provides designers with substantial headroom for implementation. Rambus and Samsung teamed to validate the HBM2E PHY and Memory Controller IP in silicon using Samsung\u2019s 14\/11nm process and advanced packaging technologies.<\/p>\n<p>\u201cWith silicon operation up to 3.2 Gbps, customers can implement HBM2E memory subsystems with the confidence of ample margin for their designs,\u201d said Matt Jones, general manager of IP Cores at Rambus. \u201cOur customers benefit from our comprehensive support that includes 2.5D package and interposer reference designs, helping ensure first-time-right implementations.\u201d<\/p>\n<p><strong>Benefits of the Rambus HBM2E Memory Interface (PHY and Controller):<\/strong><\/p>\n<ul>\n<li>Achieves speed of 3.2 Gbps per pin, delivering a system bandwidth of 410 GB\/s from a single HBM2E DRAM 3D device.<\/li>\n<li>Fully-integrated and verified in silicon <a href=\"https:\/\/www.rambus.com\/interface-ip\/ddrn-phys\/hbm\/\">HBM2E PHY<\/a> and <a href=\"https:\/\/www.rambus.com\/interface-ip\/controllers\/memory-controllers\/hbm2\/\">Controller<\/a> reduces ASIC design complexity and speeds time to market<\/li>\n<li>Includes 2.5D package and interposer reference design as part of IP license<\/li>\n<li>Provides access to Rambus system and SI\/PI experts helping ASIC designers to ensure maximum signal and power integrity for devices and systems<\/li>\n<li>Features LabStation\u2122 development environment that enables quick system bring-up, characterization and debug<\/li>\n<li>Supports high-performance applications including state-of-the-art AI\/ML training and high-performance computing (HPC) systems<\/li>\n<\/ul>\n<p>For more information on the Rambus Interface IP, including our PHYs and Controllers, please visit\u00a0<a href=\"https:\/\/www.rambus.com\/interface-ip\/\">rambus.com\/interface-ip<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Highlights:\u00a0 Supports\u00a0accelerators requiring terabyte-scale bandwidth for artificial intelligence\/machine learning (AI\/ML) training applications Fully-integrated HBM2E memory interface subsystem, consisting of verified PHY and controller, silicon proven on advanced Samsung 14\/11nm FinFET process Backed by unrivaled system expertise supporting customers with interposer and package reference designs to speed time to market SAN JOSE, Calif. \u2013\u00a0April 21, 2021\u00a0\u2013\u00a0Rambus [&hellip;]<\/p>\n","protected":false},"author":6,"featured_media":23439,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":"","_links_to":"","_links_to_target":""},"categories":[26089,475,479,34],"tags":[],"class_list":{"0":"post-60209","1":"post","2":"type-post","3":"status-publish","4":"format-standard","5":"has-post-thumbnail","7":"category-press-releases-controllers","8":"category-memory-interface","9":"category-ddrn-phys","10":"category-pressreleases","11":"entry"},"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.9 (Yoast SEO v26.9) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Rambus Expands High-Performance Memory Subsystem Offerings with HBM2E Solution on Samsung 14\/11nm - Rambus<\/title>\n<meta name=\"description\" content=\"Rambus announced the\u00a0Rambus\u00a0HBM2E memory interface subsystem,\u00a0consisting of a fully-integrated PHY and controller, is silicon proven on Samsung\u2019s advanced 14\/11nm FinFET process.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.rambus.com\/rambus-expands-high-performance-memory-subsystem-offerings-with-hbm2e-solution-on-samsung-14-11nm\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Rambus Expands High-Performance Memory Subsystem Offerings with HBM2E Solution on Samsung 14\/11nm\" \/>\n<meta property=\"og:description\" content=\"Highlights:\u00a0 Supports\u00a0accelerators requiring terabyte-scale bandwidth for artificial intelligence\/machine learning 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