{"id":59034,"date":"2019-05-13T16:01:15","date_gmt":"2019-05-13T23:01:15","guid":{"rendered":"https:\/\/nwlogic.com\/?p=59034"},"modified":"2024-06-18T11:41:47","modified_gmt":"2024-06-18T18:41:47","slug":"esilicon_combo_phy_hbm2_hbm2e_low_latency","status":"publish","type":"post","link":"https:\/\/www.rambus.com\/esilicon_combo_phy_hbm2_hbm2e_low_latency\/","title":{"rendered":"eSilicon Tapes Out 7nm Combo PHY (HBM2\/HBM2E\/Low Latency) Test Chip"},"content":{"rendered":"

Chip facilitates continued support of the latest HBM technologies for eSilicon\u2019s 2.5D FinFET ASICs<\/em><\/p>\n

SAN JOSE, Calif. \u2014 May 9, 2019<\/strong> \u2014 eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the tapeout of a 7nm test chip to provide silicon validation of its physical interface (PHY) to support the new JEDEC standard JESD235B, referred to informally as high bandwidth memory (HBM) 2E and emerging low-latency HBM technology. \u00a0The chip contains a 7nm PHY from eSilicon and a controller from Northwest Logic. \u00a0This 7nm test chip, along with a previously taped out 7nm test chip will be part of a 2.5D test system to verify end-to-end support for the new HBM interfaces. The PHY design is a \u201ccombo\u201d device that supports HBM2, HBM2E and the emerging low-latency HBM interface in one physical IP block.<\/p>\n

When compared to HBM2, the HBM2E standard increases total capacity from 8GB to 16GB, bandwidth per pin from 2.4 Gb\/s to 3.2 Gb\/s and bandwidth per stack from 307.2 GB\/s to 410 GB\/s. Samsung Electronics announced the industry\u2019s first HBM2E to deliver the 3.2 Gb\/s per-pin transfer speed, <\/a>at NVIDIA\u2019s GPU Technology Conference in March.<\/p>\n

Low latency HBM devices have been launched by Renesas Electronics<\/a>. These devices leverage Renesas low latency memory technology to realize high random-access rate and small data granularity as well as high bandwidth for latency-sensitive applications.<\/p>\n

\u201cWe are pleased to work with our partner, eSilicon, on the validation of our Controller for HBM2E and low latency applications,\u201d said Brian Daellenbach, president of Northwest Logic. \u201cThis validation further strengthens our industry-leading HBM2 Controller solution.\u201d<\/p>\n

\u201cHBM memory stacks are a critical component for many of our new FinFET-class 2.5D ASICs,\u201d said Hugh Durdan, vice president, strategy and products at eSilicon. \u201cWe look forward to validating the performance and functionality of our combo PHY and Northwest Logic\u2019s controller to support the latest HBM capabilities.\u201d<\/p>\n

Read our primer on:<\/strong>
\nHBM2E Implementation & Selection – The Ultimate Guide \u00bb<\/a><\/p>\n

You can learn more about eSilicon\u2019s 7nm IP platform here<\/a>, or contact your eSilicon sales representative directly or via sales@esilicon.com<\/a>. You can learn more about Northwest Logic\u2019s HBM2 Controller Cores here.<\/p>\n

Contacts:<\/strong>
\nSally Slemons
\neSilicon Corporation
\nsslemons@esilicon.com<\/a><\/p>\n

Nanette Collins
\nPublic Relations for eSilicon
\nnanette@nvc.com<\/a><\/p>\n

About eSilicon:<\/strong><\/p>\n

eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G\/112G SerDes plus networking-optimized 16\/14\/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I\/O libraries. Our neuASIC\u2122 platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com<\/a><\/p>\n

Collaborate. Differentiate. Win.\u2122<\/em><\/strong><\/p>\n

###<\/em><\/strong><\/p>\n

eSilicon is a registered trademark, and the eSilicon logo, neuASIC and \u201cCollaborate. Differentiate. Win.\u201d are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.<\/em><\/p>\n","protected":false},"excerpt":{"rendered":"

Chip facilitates continued support of the latest HBM technologies for eSilicon\u2019s 2.5D FinFET ASICs SAN JOSE, Calif. \u2014 May 9, 2019 \u2014 eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the tapeout of a 7nm test chip to provide silicon validation of its physical interface (PHY) […]<\/p>\n","protected":false},"author":10,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":"","_links_to":"","_links_to_target":""},"categories":[26101,26102,35],"tags":[],"class_list":{"0":"post-59034","1":"post","2":"type-post","3":"status-publish","4":"format-standard","6":"category-26101","7":"category-26102","8":"category-rambus-news","9":"entry"},"yoast_head":"\nMixel MIPI C-PHY\/D-PHY Combo IP integrated into Synaptics VXR7200 IC enabling next generation VR headsets<\/title>\n<meta name=\"description\" content=\"Mixel MIPI\u00ae IP integrated into Synaptics\u2019 VXR7200 DisplayPort to Dual MIPI VR Bridge IC\" \/>\n<meta name=\"robots\" content=\"index, follow, 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