{"id":25117,"date":"2020-09-09T14:02:30","date_gmt":"2020-09-09T21:02:30","guid":{"rendered":"https:\/\/www.rambus.com\/?p=25117"},"modified":"2020-11-18T05:29:17","modified_gmt":"2020-11-18T13:29:17","slug":"rambus-advances-hbm2e-performance-to-4-0-gbps-for-ai-ml-training-applications","status":"publish","type":"post","link":"https:\/\/www.rambus.com\/rambus-advances-hbm2e-performance-to-4-0-gbps-for-ai-ml-training-applications\/","title":{"rendered":"Rambus Advances HBM2E Performance to 4.0 Gbps for AI\/ML Training Applications"},"content":{"rendered":"<p><strong>Highlights:\u00a0<\/strong><\/p>\n<ul>\n<li><em>Fully-integrated HBM2E memory interface solution, consisting of verified PHY and controller, achieves industry\u2019s fastest performance <\/em><\/li>\n<li><em>New benchmark in performance supports\u00a0accelerators requiring terabyte-scale bandwidth for artificial intelligence\/machine learning (AI\/ML) training applications<\/em><\/li>\n<li><em>Partners with SK hynix and Alchip to develop 2.5D HBM2E memory system solution using TSMC N7 process and CoWoS<\/em><sup>\u00ae<\/sup><em> advanced packaging technologies<\/em><\/li>\n<li><em>Offers unrivaled system expertise supporting customers with interposer and package reference designs to speed time to market\n<p><strong>Read first our primer on:<\/strong><br \/>\n<a href=\"https:\/\/www.rambus.com\/blogs\/hbm2e\/\">HBM2E Implementation &amp; Selection &#8211; The Ultimate Guide \u00bb<\/a><br \/>\n<\/em><\/li>\n<\/ul>\n<figure id=\"attachment_25118\" aria-describedby=\"caption-attachment-25118\" style=\"width: 932px\" class=\"wp-caption aligncenter\"><img fetchpriority=\"high\" decoding=\"async\" class=\"size-full wp-image-25118\" src=\"https:\/\/www.rambus.com\/wp-content\/uploads\/2020\/09\/hbm2e-4g.jpg\" alt=\"Figure 1 Rambus HBM2E Interface 4 Gbps Transmit Eye\" width=\"932\" height=\"410\" srcset=\"https:\/\/www.rambus.com\/wp-content\/uploads\/2020\/09\/hbm2e-4g.jpg 932w, https:\/\/www.rambus.com\/wp-content\/uploads\/2020\/09\/hbm2e-4g-300x132.jpg 300w, https:\/\/www.rambus.com\/wp-content\/uploads\/2020\/09\/hbm2e-4g-150x66.jpg 150w, https:\/\/www.rambus.com\/wp-content\/uploads\/2020\/09\/hbm2e-4g-768x338.jpg 768w\" sizes=\"(max-width: 932px) 100vw, 932px\" \/><figcaption id=\"caption-attachment-25118\" class=\"wp-caption-text\">Figure 1 Rambus HBM2E Interface 4 Gbps Transmit Eye<\/figcaption><\/figure>\n<p><strong>SAN JOSE, Calif. \u2013\u00a0Sept. 9, 2020\u00a0<\/strong>\u2013 <a href=\"https:\/\/www.rambus.com\/\">Rambus Inc.<\/a>\u00a0(NASDAQ:\u00a0<a href=\"https:\/\/finance.yahoo.com\/quote\/rmbs?ltr=1\">RMBS<\/a>), a premier silicon IP and chip provider making data faster and safer, today announced it has achieved a record 4 Gbps performance with the <a href=\"https:\/\/www.rambus.com\/interface-ip\/ddrn-phys\/hbm\/\">Rambus\u00a0HBM2E memory interface solution<\/a> consisting of a fully-integrated PHY and controller. Paired with the industry\u2019s fastest HBM2E DRAM from SK hynix operating at 3.6 Gbps, the solution can deliver 460 GB\/s of bandwidth from a single HBM2E device. This performance meets the terabyte-scale bandwidth needs of accelerators targeting the most demanding AI\/ML training and high-performance computing (HPC) applications.<\/p>\n<p>\u201cWith this achievement by Rambus, designers of AI and HPC systems can now implement systems using the world\u2019s fastest HBM2E DRAM running at 3.6 Gbps from SK hynix,\u201d said Uksong Kang, vice president of product planning at SK hynix. \u201cIn July, we announced full-scale mass-production of HBM2E for state-of-the-art computing applications demanding the highest bandwidth available.\u201d<\/p>\n<p>The fully-integrated, production-ready Rambus HBM2E memory subsystem runs at 4 Gbps without PHY voltage overdrive. Rambus teamed with SK hynix and Alchip to implement the HBM2E 2.5D system to validate in silicon the Rambus HBM2E PHY and Memory Controller IP using TSMC\u2019s N7 process and CoWoS<sup>\u00ae<\/sup> (Chip-on-Wafer-on-Substrate) advanced packaging technologies. Co-designing with the engineering team from Rambus, Alchip led the interposer and package substrate design.<\/p>\n<p>\u201cThis advancement of Rambus and its partners, using TSMC\u2019s advanced process and packaging technologies, is another important achievement of our ongoing collaboration with Rambus,\u201d said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. \u201cWe look forward to a continued partnership with Rambus to enable the highest performance in AI\/ML and HPC applications.\u201d<\/p>\n<p>\u201cAlchip brought a demonstrated track record of success in 7nm and 2.5D package design to this initiative,\u201d said Johnny Shen, CEO of Alchip Technologies. \u201cWe\u2019re extremely proud of our contributions to Rambus\u2019 breakthrough achievement.\u201d<\/p>\n<p>Rambus has 30 years of high-speed memory design applied to the most demanding computing applications. Its renowned signal integrity expertise was key to achieving an HBM2E memory interface capable of 4 Gbps operation. This raises a new benchmark for meeting the insatiable bandwidth requirements of AI\/ML training.<\/p>\n<p>\u201cWith silicon operation up to 4 Gbps, designers can future-proof their HBM2E implementations and can be confident of ample margin for 3.6 Gbps designs,\u201d said Matthew Jones, senior director and general manager of IP cores at Rambus. \u201cAs part of every customer engagement, Rambus provides reference designs for the 2.5D package and interposer to ensure first-time right implementations for mission-critical AI\/ML designs.\u201d<\/p>\n<p><strong>Benefits of the Rambus HBM2E Memory Interface (PHY and Controller):<\/strong><\/p>\n<ul>\n<li>Achieves the industry\u2019s highest speed of 4 Gbps per pin, delivering a system bandwidth of 460 GB from a single 3.6 Gbps HBM2E DRAM 3D device.<\/li>\n<li>Fully-integrated and verified HBM2E PHY and Controller reduces ASIC design complexity and speeds time to market<\/li>\n<li>Includes 2.5D package and interposer reference design as part of IP license<\/li>\n<li>Provides access to Rambus system and SI\/PI experts helping ASIC designers to ensure maximum signal and power integrity for devices and systems<\/li>\n<li>Features LabStation\u2122 development environment that enables quick system bring-up, characterization and debug<\/li>\n<li>Supports high-performance applications including state-of-the-art AI\/ML training and high-performance computing (HPC) systems<\/li>\n<\/ul>\n<p>For more information on the Rambus Interface IP, including our PHYs and Controllers, please visit\u00a0<a href=\"https:\/\/www.rambus.com\/interface-ip\/\">rambus.com\/interface-ip<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Highlights:\u00a0 Fully-integrated HBM2E memory interface solution, consisting of verified PHY and controller, achieves industry\u2019s fastest performance New benchmark in performance supports\u00a0accelerators requiring terabyte-scale bandwidth for artificial intelligence\/machine learning (AI\/ML) training applications Partners with SK hynix and Alchip to develop 2.5D HBM2E memory system solution using TSMC N7 process and CoWoS\u00ae advanced packaging technologies Offers unrivaled [&hellip;]<\/p>\n","protected":false},"author":6,"featured_media":24882,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":"","_links_to":"","_links_to_target":""},"categories":[475,479,34],"tags":[],"class_list":{"0":"post-25117","1":"post","2":"type-post","3":"status-publish","4":"format-standard","5":"has-post-thumbnail","7":"category-memory-interface","8":"category-ddrn-phys","9":"category-pressreleases","10":"entry"},"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.9 (Yoast SEO v26.9) - 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