{"id":22123,"date":"2019-02-07T15:00:49","date_gmt":"2019-02-07T23:00:49","guid":{"rendered":"https:\/\/www.rambus.com\/?page_id=22123"},"modified":"2026-01-27T20:39:02","modified_gmt":"2026-01-28T04:39:02","slug":"crypto-accelerator-cores","status":"publish","type":"page","link":"https:\/\/www.rambus.com\/security\/crypto-accelerator-cores\/","title":{"rendered":"Crypto Accelerator Cores"},"content":{"rendered":"\t\t
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Crypto Accelerator IP<\/h1>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Offload and accelerate cryptographic processing<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Home<\/a><\/span><\/span><\/p>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Crypto Accelerator and Random Number Generator IP<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\t\t\t\t\t\tRambus offers a broad portfolio of cryptographic accelerator IP cores for symmetric and asymmetric ciphers, Hash- and HMAC-based integrity algorithms, as well as true random number generators. Rambus also offers a broad portfolio of DPA and FIA protected cryptographic accelerators<\/a>. The cores that accelerate NIST cryptographic algorithms are validated to FIPS 140-2 and FIPS 140-3 CAVP. A Common Criteria-EAL4+ core is also available.\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\t\t\t\t\t\tSCA Resistant Crypto Accelerator IP<\/a>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\t\t\t\t\t\tQuantum Safe Crypto Accelerator IP<\/a>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\t\t\t\t\t\tPublic Key Accelerator IP<\/a>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\t\t\t\t\t\tLightweight Crypto Accelerator IP<\/a>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\t\t\t\t\t\tCipher Accelerator IP<\/a>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\t\t\t\t\t\tHash and HMAC Accelerator IP<\/a>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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SCA Resistant Crypto Accelerator IP<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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When integrated into an SoC, the Rambus Side Channel Attack (SCA) Resistant hardware cores offer DPA resistance to prevent the leakage of secret cryptographic key material through attacks. In addition, the cores with Fault Injection Attack (FIA) resistance options offer protection against faults induced by laser or EM probing, voltage and or clock glitching. These superior performance cores are easy to integrate into SoCs and FPGAs, providing robust side-channel resistance across different security and performance levels.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Solution<\/th>Description<\/th><\/tr><\/thead>
QSE-IP-86-DPA<\/a><\/td>Fast Quantum Safe Engine for ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium) with DPA<\/td><\/tr>
PKE-IP-85-DPA(-FIA)<\/a><\/td>Fast Public Key Engine with DPA or with DPA and FIA<\/td><\/tr>
AES-IP-3X-DPA(-FIA)<\/a><\/td>AES Authenticated Encryption Accelerator with DPA or with DPA and FIA<\/td><\/tr>
ICE-338-DPA<\/a><\/td>Fast Inline Cipher Engine, AES-XTS\/GCM, SM4-XTS\/GCM, DPA<\/td><\/tr>
HMAC-SHA-256-DPA<\/td>HMAC SHA-2 engine, 224 & 256 Mode, DPA<\/td><\/tr>
HMAC-SHA-256-512-DPA<\/td>HMAC SHA-2 engine, 224, 256, 384 & 512 Mode, DPA<\/td><\/tr>
HMAC-IP-59-DPA<\/td>SHA-3 engine w\/ HMAC, DPA SHA-3\/SHAKE\/cSHAKE\/KMAC<\/td><\/tr>
SHA-IP-57-DPA<\/td>SHA-3 engine, w\/o HMAC, DPA SHA-3\/SHAKE\/cSHAKE\/KMAC<\/td><\/tr><\/tbody><\/table>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Back to Top<\/a><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Quantum Safe Crypto Accelerator IP<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Standalone hardware IP cores providing Quantum Safe Cryptography acceleration for ASIC, SoC and FPGA implementation.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Solution<\/th>\nDescription<\/th>\n<\/tr>\n<\/thead>\n
QSE-IP-86<\/a><\/td>\nFast Quantum Safe Engine for ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium)<\/td>\n<\/tr>\n
QSE-IP-86-DPA<\/a><\/td>\nFast Quantum Safe Engine for ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium) with DPA<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Back to Top<\/a><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Lightweight Crypto Accelerator IP<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Standalone hardware IP core for the NIST lightweight cryptographic AEAD and Hash algorithms.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Solution<\/th>\nDescription<\/th>\n<\/tr>\n<\/thead>\n
ASCON-IP-41<\/a><\/td>\nNIST\u2019s ASCON Lightweight Crypto Algorithm Accelerator<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Back to Top<\/a><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Random Number Generator IP<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Standalone True Random Number Generator (TRNG) and Non-deterministic Random Bit Generator (NRBG) cores.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Solution<\/th>\nDescription<\/th>\n<\/tr>\n<\/thead>\n
TRNG-IP-76<\/a><\/td>\nNIST ESV certified, AIS-31, FIPS (SP800-90A\/B\/C) Cellular Automata-based True Random Number Generator<\/td>\n<\/tr>\n
CRNG-IP-77<\/a><\/td>\nFast NIST ESV certified, FIPS (SP800-90A\/B\/C) Cellular Automata-based True Random Number Generator<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Back to Top<\/a><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Public Key Accelerator IP<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Standalone hardware IP cores for public key-based operations like digital signature verification, key exchange, authentication, and key generation.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Solution<\/th>\nDescription<\/th>\n<\/tr>\n<\/thead>\n
QSE-IP-86<\/a><\/td>\nFast Quantum Safe Engine for ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium)<\/td>\n<\/tr>\n
PKE-IP-85-DPA(-FIA)<\/a><\/td>\nFast Public Key Engine with DPA or DPA and FIA<\/td>\n<\/tr>\n
PKE-IP-85f<\/td>\nUltra-Fast Public Key Engine<\/td>\n<\/tr>\n
PKE-IP-85f-x<\/td>\nFarm of x * Ultra-Fast Public Key Engines<\/td>\n<\/tr>\n
PKA-IP-28<\/a><\/td>\nSmall RSA\/ECC Public Key Accelerators<\/td>\n<\/tr>\n
PKA-IP-150<\/a><\/td>\nRSA\/ECC Public Key Accelerators with TRNG and AHB<\/td>\n<\/tr>\n
PKI-IP-154<\/td>\nRSA\/ECC Public Key Accelerator Farm with TRNG and AHB<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Back to Top<\/a><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Cipher Accelerator IP<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Standalone hardware IP cores for symmetric cryptographic primitive algorithms.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Solution<\/th>\nDescription<\/th>\n<\/tr>\n<\/thead>\n
AES-IP-36<\/a><\/td>\nAES ECB\/CBC\/CTR Accelerators<\/td>\n<\/tr>\n
AES-IP-37<\/a><\/td>\nAES Key Wrap Accelerators<\/td>\n<\/tr>\n
AES-IP-38<\/a><\/td>\nAES XTS\/GCM Accelerators<\/td>\n<\/tr>\n
AES-IP-39<\/a><\/td>\nAES \u201cAll Modes\u201d Accelerators<\/td>\n<\/tr>\n
AES-IP-61<\/a><\/td>\nAES-GCM Pipeline<\/td>\n<\/tr>\n
Kasumi-IP-06<\/a><\/td>\n3GPP Kasumi Accelerators<\/td>\n<\/tr>\n
SNOW-IP-46<\/a><\/td>\n3GPP SNOW 3G Accelerators<\/td>\n<\/tr>\n
ZUC-IP-48<\/a><\/td>\n3GPP ZUC Accelerators<\/td>\n<\/tr>\n
SM4-IP-12<\/td>\nSM4 ECB\/CBC\/CTR Accelerators<\/td>\n<\/tr>\n
SM4-IP-40<\/td>\nSM4 \u201cAll Modes\u201d Accelerators<\/td>\n<\/tr>\n
ChaCha-IP-13<\/a><\/td>\nChaCha20 Accelerators<\/td>\n<\/tr>\n
3DES-IP-16<\/a><\/td>\n3DES ECB\/CBC Accelerators<\/td>\n<\/tr>\n
ARC4-IP-44<\/a><\/td>\nARC4 Stream Cipher Accelerators<\/td>\n<\/tr>\n
CRYPT-IP-120<\/a><\/td>\nAES Crypto and SHA-2 Hash Core with DMA<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Back to Top<\/a><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Hash and HMAC Accelerator IP<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Standalone hardware IP cores for Hash and HMAC-based integrity algorithms.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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Solution<\/th>\nDescription<\/th>\n<\/tr>\n<\/thead>\n
HASH-IP-57<\/a><\/td>\nSHA-3, SHA-2, SHA-1, SM3, MD5, Hash Accelerators<\/td>\n<\/tr>\n
HMAC-IP-59<\/a><\/td>\nSHA-3, SHAKE, cSHAKE, SHA-2, SHA-1, SM3, MD5 Hash-based HMAC and KMAC Accelerators<\/td>\n<\/tr>\n
SM3-IP-52<\/td>\nChinese SM3 Accelerators<\/td>\n<\/tr>\n
POLY-IP-53<\/a><\/td>\nPoly1305-based MAC Accelerators<\/td>\n<\/tr>\n
WHIRLPOOL-IP-51<\/td>\nWhirlpool Accelerators<\/td>\n<\/tr>\n
CRYPT-IP-120<\/a><\/td>\nSHA-2 Hash Core with DMA<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Back to Top<\/a><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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Lightweight Cryptography: An Introduction<\/h3>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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The National Institute of Standards and Technology (NIST) announced on February 7, 2023, that it had selected the ASCON algorithm to become the standard for Lightweight Cryptography. In this whitepaper, we will explore what lightweight cryptography is and why it is worth considering for specific Internet of Things (IoT) use cases.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

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\n\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\tDownload White Paper<\/span>\n\t\t\t\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tUltra Ethernet Security: Protecting AI\/HPC at Scale\t\t\t<\/a>\n\t\t<\/h3>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tSecuring the Future of Terabit Ethernet: Introducing the Rambus Multi-Channel Engine MACsec-IP-364 (+363)\t\t\t<\/a>\n\t\t<\/h3>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tBringing IPsec into the Quantum Safe Era\t\t\t<\/a>\n\t\t<\/h3>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/article>\n\t\t\t\t<\/div>\n\t\t\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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News<\/h4>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tRambus Enhances Data Center and AI Protection with Next-Gen CryptoManager Security IP Solutions\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tRambus Protects Data Center Infrastructure with Quantum Safe Engine IP\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tRambus Safeguards Accelerated Computing with FPGA-targeted Security IP\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t<\/div>\n\t\t\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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Papers<\/h4>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tMACsec Fundamentals\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tSecuring Automotive Ethernet with MACsec Silicon IP\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tProtecting Data and Devices Now and in the Quantum Computing Era\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t<\/div>\n\t\t\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t
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Webinars<\/h4>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tSecure by Design Series: UEC Security: Delivering High-Performance, Scalability and Secure Networking for AI and HPC\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tSecure by Design Series: Security Certifications: Navigating Standards, Requirements, and Market Expectations\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t
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\n\t\t\t\n\t\t\t\tSecure by Design Series: Preparing for the Quantum Era: Practical Approaches to Quantum Safe Cryptography\t\t\t<\/a>\n\t\t<\/h4>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t<\/div>\n\t\t\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"

Crypto Accelerator IP Offload and accelerate cryptographic processing Contact Us Crypto Accelerator and Random Number Generator IP Rambus offers a broad portfolio of cryptographic accelerator<\/p>\n","protected":false},"author":6,"featured_media":62736,"parent":13315,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"template-full.php","meta":{"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":"","_links_to":"","_links_to_target":""},"tags":[],"class_list":{"0":"post-22123","1":"page","2":"type-page","3":"status-publish","4":"has-post-thumbnail","6":"entry"},"yoast_head":"\nHardware Cryptographic Accelerators - DPA Countermeasures | Rambus<\/title>\n<meta name=\"description\" content=\"Symmetric & asymmetric ciphers. Hash & HMAC-based integrity algorithms. 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