Table of Contents:

• • About BOS Semiconductors
  • Target Markets
  • Eagle-N: A Breakthrough in Automotive AI
  • Why Hardware Security Matters
  • Rambus RT-640: ASIL-B Certified Security for Eagle-N
  • The Strategic Impact
  • Summary

About BOS Semiconductors

Founded in 2022, BOS Semiconductors—short for Best of Silicon—is a global fabless semiconductor company headquartered in South Korea. Its mission is to drive mobility innovation through differentiated semiconductor technology, focusing on:

• Technology Excellence: Advanced chiplet-based SoCs for automotive and robotics.
• Distinguished Creativity: Reimagining mobility with modular, scalable architectures.
• Safety and Reliability: Meeting stringent automotive standards for functional safety and cybersecurity.

Target Markets

BOS primarily serves:

• Automotive ADAS and IVI systems – enabling real-time AI processing for safety and immersive experiences.
• Autonomous driving platforms – delivering scalable compute for Level 2+ autonomy.
• Robotics and intelligent spaces – extending AI acceleration beyond vehicles into drones and industrial automation.

Eagle-N: A Breakthrough in Automotive AI

The Eagle-N chiplet SoC, is designed to meet the growing compute demands of modern vehicles:

• Performance: Up to 250 TOPS (INT8) NPU performance, scalable to 2,000+ TOPS.
• Architecture: Chiplet-based design for modularity and cost efficiency
• Interfaces: PCIe Gen5 and UCIe for seamless integration with existing ADAS and IVI processors.
• Safety: ISO 26262 ASIL-B compliance and AEC-Q100 Grade 2 qualification.
• Security: Built-in hardware virtualization and security engine.

This architecture allows OEMs and Tier-1 suppliers to add AI acceleration without redesigning entire systems, reducing cost and time-to-market.

Why Hardware Security Matters

As vehicles become software-defined and connected, cybersecurity is no longer optional—it’s a core safety requirement. Two critical standards govern this domain:

• ISO 26262: Functional safety for electrical/electronic systems, defining Automotive Safety Integrity Levels (ASILs).
• ISO/SAE 21434: Cybersecurity engineering for road vehicles, addressing threats across the entire lifecycle.

Failure to comply can lead to catastrophic risks—from system malfunctions to remote cyberattacks that compromise steering or braking. For chipmakers, this means embedding security by design at the silicon level.

Rambus RT-640: ASIL-B Certified Security for Eagle-N

To meet these stringent requirements, BOS integrates Rambus RT-640, an automotive-grade Embedded HSM that provides:

• Root-of-Trust security: providing system wide Root-of-Trust based security functionality such as secure boot, debug and firmware update, key management and protection, attestation, SKU and feature management, cryptographic acceleration.  
• ASIL-B Certification: TÜV-SGS certified per ISO 26262, ensuring functional safety.
• Cryptographic Strength: Hardware accelerators for AES, RSA, ECC, HMAC-SHA-2, and NIST-compliant random number generation.
• Fault Protection: Detects ≥90% single-point faults and ≥60% latent faults, meeting ASIL-B metrics.
• Secure Boot & Key Management: Guarantees that only authenticated software runs on the SoC.
• Anti-Tamper Mechanisms: Protects against physical and side-channel attacks.

This integration ensures Eagle-N delivers robust AI performance with uncompromising security, enabling OEMs to comply with global safety and cybersecurity regulations.

The Strategic Impact

The BOS-Rambus collaboration sets a new benchmark for automotive silicon:

• For OEMs and Tier-1s: Accelerates deployment of advanced AI features while meeting ISO 26262 and ISO/SAE 21434 compliance.
• For Consumers: Safer, smarter, and more secure vehicles—paving the way for autonomous mobility.
• For the Industry: Demonstrates how chiplet architectures and hardware-rooted security can coexist to deliver scalable, future-ready solutions.

Conclusion

As the automotive world continues toward autonomy and connectivity, performance without security is no longer acceptable. BOS Semiconductors’ Eagle-N, fortified by Rambus RT-640, exemplifies the fusion of high-performance AI and ASIL-B certified security—a critical foundation for the next generation of vehicles.

Anti-tamper sensors are an essential tool among several defenses used to protect against these security threats. By continuously monitoring for abnormal environmental or electrical conditions, anti-tamper sensors help ensure that when a device is touched, opened, glitched, or zapped, your security stack knows and reacts to protect your system.

The Modern Tamper Landscape

Today’s adversaries use voltage glitching to skip instructions, clock manipulation to desynchronize logic, and electromagnetic fault injection (EMFI) to flip bits at precise moments. They may also use strong magnets or environmental shifts to blind sensors or disrupt measurements, especially in metering and industrial systems.

Why does this matter? Because hardware secrets (keys, certificates) underpin secure boot, encrypted communications, and software trust. Physical compromise of just one device can open a backdoor to a much larger network if unique per device protections and real-time tamper responses aren’t in place.

The Top Customer Pain Points

From conversations with SoC designers, several recurring challenges emerge:

1. Evolving attack techniques
   Digital-only countermeasures often miss analog domain faults like voltage, clock, and EMFI attacks. Teams need diverse, low latency sensors that can spot subtle, nanosecond scale anomalies before damage is done.
2. Integration across process nodes and foundries
   Analog IP is traditionally process specific, making portability painful when supply constraints or costs push a design to another process node or foundry. Reengineering slows releases and consumes scarce analog engineering talent.
3. Tuning and false positives and negatives
   Tamper sensors must be sensitive without being noisy. Poor thresholding or inadequate environmental compensation can trigger needless shutdowns, or worse, miss an actual attack. Getting that balance right demands robust IP and good system architecture
4. Compliance pressure
   Regulations and certifications (e.g., FIPS 140-3 Level 3 and 4, Common Criteria High Assurance Levels, SESIP L3, ISO 21434) add requirements for key protection,  tamper responses, and secure boot. Meeting them while hitting power, area, and schedule targets is hard.

What a “Good” system Looks Like: Principles of Anti-tamper by Design

A resilient anti-tamper strategy embraces sensor diversity, secure event handling, and automated responses:

• Multi‑modal sensing (voltage, clock, temperature, magnetic/EMFI) to detect a broad spectrum of physical attacks.
• Secure response paths anchored in a hardware Root of Trust (RoT)—so detected events can trigger policy-driven actions like key zeroization, boot lockdown, or secure telemetry, even if an application code is compromised.
• Per device uniqueness (unique keys, secure provisioning) to contain the blast radius if one unit falls into the wrong hands.

This is where Agile Analog and Rambus complement each other.

Agile Analog: Deep Tamper Detection + Prevention in the Analog Domain

Agile Analog’s agileSecure portfolio brings a comprehensive, customizable set of tamper detection IP to protect SoCs on advanced process nodes:

• agileVGLITCH – Voltage Glitch Detector: Detects nanosecond scale supply anomalies used in instruction skipping and bypass attacks.
• agileCAM – Clock Attack Monitor: Catches clock frequency shifts, holds, and glitches with programmable thresholds.
• agileTSENSE_D – Digital Temperature Sensor: Monitors abnormal thermal profiles indicative of physical interference or environmental manipulation.
• agileEMSensor – EMFI Detector: Detects electromagnetic fault injection, one of the hardest physical attack vectors to counter with digital logic alone.

Beyond tamper detection, Agile Analog’s agileSecure also offers tamper prevention IP—internally biased LDOs, bandgap references, oscillators, power-on reset and power-OK blocks—to isolate and harden critical circuits against external manipulation.

Why customers choose Agile Analog

• Process portability and time-to-market: Their digitally wrapped, process agnostic, fully verified approach helps teams seamlessly integrate analog IP blocks like digital IP, reducing re-spins across nodes/foundries and speeding SoC schedules.
• Standards alignment: Deployments are increasingly aligned with FIPS 140‑3 and Common Criteria requirements—critical for regulated markets.
• Proven on advanced process nodes: Recent deliveries include TSMC N4P engagements with a tier1 U.S. customer, underscoring maturity on cutting-edge processes.

Rambus: Hardware Root of Trust, Anti-tamper, and QuantumSafe Security

While Agile Analog monitors and hardens the physical attack surface, Rambus provides the secure control plane that decides what to do when tampering is detected.

The CryptoManager Security IP family spans Root of Trust (RoT), Hub, and Core offerings, delivering progressively higher levels of functionality and integration:

• Hardware RoT with secure boot, secure storage, and policy driven tamper responses—available from compact state machines to programmable secure coprocessors.
• Quantum‑Safe boot flow and crypto accelerators to protect against future quantum compute threats while meeting today’s performance needs.
• DPA/FIA countermeasures to resist power analysis and fault injection at the cryptographic core, complementing analog tamper detection located next to critical circuitry.
• Inline memory encryption and protocol engines (MACsec/IPsec/TLS) to protect data in use and in motion, completing a holistic data‑centric security posture.

With support for FIPS, SESIP, PSA Certified, and ISO 21434, CryptoManager solutions help teams accelerate certification and ship faster into regulated markets like automotive and data centers.

Mapping Pain Points to the Joint Solution

Implementation Checklist: Getting It Right the First Time

1. Threat model by device class. Map likely physical attacks (serviceable vs. sealed units, field vs. factory) and decide which sensors you need (voltage, clock, temp, EMFI) for layered coverage.
2. Place sensors near assets. Position voltage and clock monitors on relevant domains and route signals securely to the RoT—short paths, shielded where practical.
3. Calibrate and test. Use built-in programmability to tune thresholds across PVT corners. Run fault injection tests (voltage glitches, clock glitches, EMFI) pre and post silicon to validate coverage and false positive rates.
4. Provision uniquely, attest continuously. Unique keys and attestation to prevent a single device compromise from scaling to a fleet.
5. Plan for updates. As attacks evolve, update RoT policies and, where applicable, firmware to refine responses without re-spinning silicon.

Real‑World Momentum

Agile Analog has announced deliveries of its agileSecure anti-tamper suite—including EMFI sensing—to tier1 customers on TSMC N4P, reflecting demand for robust analog security IP on advanced process nodes. As well as tamper detection IP, the portfolio also includes tamper prevention IP (LDOs, bandgaps, POR/POK) to harden critical circuits against manipulation. In parallel, Rambus introduced its nextgen CryptoManager Security IP with a three-tier architecture, QuantumSafe boot, and a broad certification roadmap—aimed squarely at data center, AI, automotive, and high assurance SoCs.

The Bottom Line

Anti-tamper sensors are non-negotiable in a world where physical attacks are mainstream. But sensors alone aren’t enough. You need a secure control plane that can decide and act, anchored in hardware, with the independent analysis that certifications bring and countermeasures to withstand both today’s and tomorrow’s threats.

• Agile Analog delivers highly configurable analog tamper detection and tamper prevention IP — portable across processes, tuned for advanced nodes, and designed to spot the faults attackers rely on.
• Rambus provides the Root of Trust and cryptographic backbone—with anti-tamper hardening, QuantumSafe readiness, and a proven path to compliance.

Together, they offer a defense in depth blueprint that addresses customer pain points comprehensively: better detection, simpler integration, fewer false positives, and smoother certification. If your roadmap includes secure SoCs for AI, automotive, industrial, or payments, pairing  Agile Analog’s agileSecure with Rambus CryptoManager is a pragmatic way to raise the bar.

Quantum computers will eventually become powerful enough to break public key-based cryptography, also known as asymmetric cryptography. Public key-based cryptography is used to protect everything from your online communications to your financial transactions.

Quantum computing represents a major security threat and action is needed now to secure applications and infrastructure using Post-Quantum/Quantum Safe Cryptography.

This blog explains everything you need to know about the new algorithms designed to protect against quantum computer attacks.

Table of Contents

• What is quantum computing?
• Why are quantum computers a security threat?
• What is Post-Quantum Cryptography (PQC)?
• Is Quantum Safe Cryptography the same as Post-Quantum Cryptography (PQC)?
• Why do we need to act now if quantum computers are still a way off?
• What progress has been made to develop new PQC algorithms?
• What recommendations does CNSA 2.0 make for transitioning to PQC algorithms?
• How can companies get ready for the Quantum Computing Era?
• What Quantum Safe IP solutions are available from Rambus?

What is quantum computing?

Quantum computing utilizes quantum mechanics to solve certain classes of complex problems faster than is possible on classic computers. Problems that currently take the most powerful supercomputer several years could potentially be solved in days.

Source: Quantum Could Solve Countless Problems —And Create New Ones | Time, February 2023

As such, quantum computers have the potential to deliver the computational power that could take applications like AI to a whole new level. Powerful quantum computers will become a reality in the not-so-distant future, and while they offer many benefits, they also present a major security threat.

Why are quantum computers a security threat?

Once sufficiently powerful quantum computers exist, traditional asymmetric cryptographic methods for key exchange and digital signatures will be broken. Leveraging Shor’s algorithm, quantum computers will be capable of reducing the security of discrete logarithm-based schemes like Elliptic Curve Cryptography (ECC) and factorization-based schemes like RSA (Rivest-Shamir-Adleman) so much that no reasonable key size would suffice to keep data secure. ECC and RSA are the algorithms used to protect everything from our bank accounts to our medical records.

Governments, researchers, and tech leaders the world over have recognized this quantum threat and the difficulty in securing critical infrastructure against attacks from quantum computers.

“A quantum computer of sufficient size and sophistication — also known as a cryptanalytically relevant quantum computer (CRQC) — will be capable of breaking much of the public-key cryptography used on digital systems across the United States and around the world.

When it becomes available, a CRQC could jeopardize civilian and military communications, undermine supervisory and control systems for critical infrastructure, and defeat security protocols for most Internet-based financial transactions.”

National Security Memorandum on Promoting United States Leadership in Quantum Computing While Mitigating Risks to Vulnerable Cryptographic Systems, May 2022

What is Post-Quantum Cryptography (PQC)?

New digital signatures and key encapsulation mechanisms (KEMs) are needed to protect data and hardware from quantum attacks. Many initiatives have been launched throughout the world to develop and deploy new cryptographic algorithms that can replace RSA and ECC while being highly resistant to both classic and quantum attacks. Post-Quantum Cryptography (PQC) refers to these cryptographic algorithms designed to withstand attacks by quantum computers.

Is Quantum Safe Cryptography the same as Post-Quantum Cryptography (PQC)?

Yes, Quantum Safe Cryptography is another term for Post-Quantum Cryptography. Both refer to cryptographic algorithms designed to withstand attacks by quantum computers. Other terms that you may come across include Quantum Proof Cryptography or Quantum Resistant Cryptography.

Why do we need to act now if quantum computers are still a way off?

While quantum computers powerful enough to break public key encryption may still be a way off, data harvesting is happening now. Malicious actors are already said to be collecting encrypted data and storing it for the time when future quantum computers will be capable of breaking our current encryption methods. This is known as a “harvest now, decrypt later” strategy.

Further because the shelf life of confidential or private information can span years or decades, there is a rapidly growing need to protect such data today to future proof it from quantum attack. Additionally, for many devices such as chips, the development cycle is a long one. Given that it can take years for security testing, certification and then deployment into the existing infrastructure, the earlier the transition to Quantum Safe Cryptography begins, the better.

What progress has been made to develop new PQC algorithms?

The biggest public initiative to develop and standardize new PQC algorithms was launched by The U.S. Department of Commerce’s National Institute of Standards and Technology (NIST). International teams of cryptographers submitted algorithm proposals, reviewed the proposals, broke some, and gained confidence in the security of others.

After multiple rounds of evaluations, on July 5th, 2022, NIST announced the first PQC algorithms selected for standardization. CRYSTALS-Kyber was selected as a Key Encapsulation Mechanism (KEM) and CRYSTALS-Dilithium, FALCON, and SPHINCS+ were selected as digital signature algorithms.

On August 24th, 2023, NIST announced the first three draft standards for general-purpose Quantum Safe Cryptography.

These are draft standards are:

• FIPS 203 ML-KEM: Module-Lattice-Based Key Encapsulation Mechanism Standard, which is based on the previously selected CRYSTALS-Kyber mechanism
• FIPS 204 ML-DSA: Module-Lattice-Based Digital Signature Standard, which is based on the previously selected CRYSTALS-Dilithium signature scheme
• FIPS 205 SLH-DSA: Stateless Hash-Based Digital Signature Standard, which is based on the previously selected SPHINCS+ signature scheme

What recommendations does CNSA 2.0 make for transitioning to PQC algorithms?

The National Security Agency (NSA) published an update to its Commercial National Security Algorithm Suite (CNSA) in September 2022, CNSA 2.0.

National Security Systems (NSS) will need to fully transition to PQC algorithms by 2033 and some use cases will be required to complete the transition as early as 2030. CNSA 2.0 specifies that CRYSTALS-Kyber and CRYSTALS-Dilithium should be used as quantum-resistant algorithms, along with stateful hash-based signature schemes XMSS (eXtended Merkle Signature Scheme) and LMS (Leighton-Micali Signatures).

CNSA 2.0 sets out an ambitious timeline for PQC algorithm adoption – other organizations across the globe are set to follow suit with their own guidelines.

Source: NSA Commercial National Security Algorithm Suite 2.0, September 2022

How can companies get ready for the Quantum Computing Era?

• Understand where vulnerable cryptography like RSA or ECC is deployed in your products.
• Investigate what performance impact a PQC transition will have on your products and what makes sense for your product roadmap.
• Establish what transition timelines your products must observe.
• Speak with your customers and suppliers to ensure that expectations and plans align.
• Understand where vulnerable cryptography like RSA or ECC is deployed in your business infrastructure and business processes.
• Talk to security experts like Rambus to understand how you can begin to transition to Quantum Safe Cryptography

What Quantum Safe IP solutions are available from Rambus?

Rambus Quantum Safe IP solutions offer a hardware-level security solution to protect data and hardware against quantum computer attacks using NIST and CNSA selected algorithms.

Rambus Quantum Safe IP products are compliant with FIPS 203 ML-KEM and FIPS 204 ML-DSA draft standards. Products are firmware programmable to allow for updates with evolving quantum-resistant standards.

The products can be deployed in ASIC, SoC and FPGA implementations for a wide range of applications including data center, AI/ML, defense and other highly secure applications.

Keep Reading:
– Bringing IPsec into the Quantum Safe Era
– Rambus Expands Quantum Safe Solutions with Quantum Safe Engine IP
– Rambus CryptoManager Root of Trust Solutions Tailor Security Capabilities to Specific Customer Needs with New Three-Tier Architecture

Summary

Quantum computing is being pursued across industry, government and academia with tremendous energy and is set to become a reality in the not-so-distant future. For many years, Rambus has been a leading voice in the PQC movement and now offers a portfolio of Quantum Safe IP solutions designed to offer hardware-level security using NIST and CNSA selected algorithms.

Explore more resources:
– Hardware Root of Trust: Everything you need to know
– Protecting Data and Devices Now and in the Quantum Computing Era
– Quantum Safe Cryptography: Protecting Devices and Data in the Quantum Era

In this article:

• • What is hardware root of trust?
  • What are the types of a silicon-based hardware root of trust?
  • What are the benefits of a programmable hardware root of trust?
  • What features should a programmable hardware root of trust offer?
  • What is the Rambus Root of Trust?
  • How is the Rambus Root of Trust architected for security?
  • What’s new in the latest generation of Rambus Root of Trust IP?
  • What is Quantum Safe Cryptography?
  • Is there a Root of Trust configured for my application?
  • What should I keep in mind when selecting a Root of Trust IP?

What is hardware root of trust?

A hardware root of trust is the foundation on which all secure operations of a computing system depend. It contains the keys used for cryptographic functions and enables a secure boot process. It is inherently trusted and therefore must be secure by design. The most secure implementation of a root of trust is in hardware making it immune from malware attacks. As such, it can be a stand-alone security module or implemented as security module within a processor or system on chip (SoC).

What are the types of a silicon-based hardware root of trust?

A silicon-based hardware root of trust falls into two categories: fixed function and programmable. Essentially, a fixed-function root of trust is firmware controlled. These are typically compact and designed to perform a specific set of functions like data encryption, certificate validation and key management. These compact, firmware-controlled root of trust solutions are particularly well suited for Internet of Things (IoT) devices.

In contrast, a hardware-based programmable root of trust is built around a CPU. Performing all the functions of a firmware-controlled solution, a programmable root of trust can also execute a more complex set of security functions. A programmable root of trust is versatile and upgradable, enabling it to run entirely new cryptographic algorithms and secure applications to meet evolving attack vectors.

What are the benefits of a programmable hardware root of trust?

The cybersecurity threat landscape is dynamic and rapidly evolving. Indeed, attackers are constantly finding new ways to exploit critical vulnerabilities across a wide range of applications and devices. Fortunately, a programmable hardware-based root of trust can be continuously updated to contend with an ever-increasing range of threats.

A programmable hardware-based root of trust is a key component to protect against a number of security threats, including:

• Host processor compromise
• Non-volatile memory (NVM) key extraction
• Tearing and other attacks against NVM writes
• Corruption of non-volatile memory or fuses
• Test and debug interface attacks
• Side-channel and perturbation attacks including Simple Power Analysis (SPA), Differential Power Analysis (DPA) and Fault Injection Attacks (FIA)
• Manufacturing/personalization facility compromise (insider attack)
• Man-in-the-middle and replay attacks
• Probing of external buses

What features should a programmable hardware root of trust offer?

A programmable hardware root of trust should be purpose-built; specifically designed from the ground up to provide a robust level of security. Since the root of trust is a logical target for an attacker, it should be made as secure as possible to safeguard it from compromise. Capabilities should include:

• • Siloed Execution:

    Ensures that sensitive security functions are only performed within a dedicated security domain that is physically separated from the general-purpose processor. This paradigm allows the primary CPU to be optimized for architectural complexity and performance – with security functionality safely isolated in a physically separated root of trust.

  • Comprehensive Anti-Tamper and Side-Channel Resistance:

    Protects against multiple fault injection and side-channel attacks.

  • Layered Security:

    Provides multiple layers of robust defense to avoid a single point of failure. Access to cryptographic hardware modules and other sensitive security resources are enforced in hardware, while critical keys are only available to hardware. Software security can be layered on top of a hardware-based root of trust, thereby providing additional flexibility and security.

  • Multiple Root of Trust Instances:

    Ensures isolation of resources, keys and security assets. In real-world terms, this means each entity – such as a chip vendor, OEM or service provider – has access to its own ‘virtual’ security core and performs secure functions without having to ‘trust’ other entities. This allows individual entities to possess unique root and derived keys, as well as access only to specified features and resources such as OTP, debug and control bits. Moreover, support for multiple root of trust instances enables the security core to assign or delegate permissions to other entities at any point in the device life cycle, while isolating (in hardware) unique signed apps that are siloed away from other programs.

What is the Rambus Root of Trust?

Rambus offers a catalog of robust Root of Trust solutions, ranging from richly featured military-grade co-processors to highly compact firmware-controlled. With a breadth of solutions applicable from the data center to IoT devices, Rambus has a Root of Trust solution for almost every application.

Rambus’ Parvez Shaik explains the importance of addressing supply chain vulnerabilities, the advantages of a hardware root of trust, and the new features of the third-generation CryptoManager Root of Trust products in this episode of Ask the Experts.

Jump to: Root of Trust solutions »

How is the Rambus Root of Trust architected for security?

The CryptoManager RT-6xx Root of Trust family from Rambus is the latest generation of fully programmable FIPS 140-3 compliant hardware security cores offering Quantum Safe security by design for data center and other highly secure applications. The CryptoManager RT-6xx family protects against a wide range of hardware and software attacks through state-of-the-art side channel attack countermeasures and anti-tamper and security techniques.

CryptoManager RT-6xx Series Root of Trust Block Diagram

The diagram above illustrates the basic architecture of the Rambus RT-600 series Root of Trust, including:

The CryptoManager RT-6xx Root of Trust is a siloed hardware security IP core for integration into semiconductors, offering secure execution of authenticated user applications, tamper detection and protection, secure storage and handling of keys and security assets, and optional resistance to side-channel attacks. The Root of Trust is easily integrated with industry-standard interfaces and system architectures and includes standard hardware cryptographic cores. Access to crypto modules, keys, memory ranges, I/O, and other resources is enforced in hardware. Critical operations, including key derivation and storage, are performed in hardware with no access by software. The Root of Trust is based on a custom 32-bit processor designed specifically to provide a trusted foundation for secure processing on chip and in the system.

The Root of Trust supports all common host processor architectures including ARM, RISC-V, x86 and others. The multi-threaded secure processor runs customer developed signed code either as a monolithic supervisor or as loadable security applications which include permissions and security-related metadata. It can implement standard security functionality provided by Rambus, or complete customer-specific security applications, including key and data provisioning, security protocols, biometric applications, secure boot, secure firmware update, and many more.

Keep on reading:
Rambus CryptoManager Root of Trust Solutions Tailor Security Capabilities to Specific Customer Needs with New Three-Tier Architecture

What is Quantum Safe Cryptography?

The CryptoManager RT-6xx Root of Trust series is at the forefront of a new category of programmable hardware-based security cores with its new Quantum Safe Cryptography features.

Once sufficiently powerful quantum computers exist, traditional asymmetric cryptographic methods for key exchange and digital signatures will be easily broken. New cryptographic algorithms known as quantum safe cryptography (QSC) or post-quantum cryptography (PQC) are needed to protect against quantum computer attacks.

The latest generation of Rambus Root of Trust IP offers a state-of-the-art programmable security solution to protect hardware and data with NIST and CNSA quantum-resistant algorithms. The Quantum Safe Engine operates with the CRYSTALS-Kyber and CRYSTALS-Dilithium algorithms, as well as the stateful hash-based signature schemes XMSS (eXtended Merkle Signature Scheme) or LMS (Leighton-Micali Signatures).

Learn more about Quantum Safe Cryptography:
– Post-quantum Cryptography (PQC): New Algorithms for a New Era
– Rambus Expands Quantum Safe Solutions with Quantum Safe Engine IP

Is there a Rambus Root of Trust configured for my application?

There are Rambus Root of Trust solutions tailored to address the specific security requirements and certification standards of nearly every application:

• • The RT-1xx series of Root of Trust solutions are designed for use in power and space-constrained applications as in IoT devices. Featuring a firmware-controlled architecture with dedicated secure memories, the RT-1xx hardware Root of Trust cores provide a variety of cryptographic accelerators including AES, SHA-2, RSA and ECC. There are versions which include SM2, SM3 and SM4 accelerators for the China market.
  • The CryptoManager RT-6xx is a fully programmable, FIPS 140-3 compliant, hardware security core offering security-by-design for data center cloud, AI/ML, as well as general purpose semiconductor applications. It protects against a wide range of hardware and software attacks through state-of-the-art anti-tamper and security techniques.
  • The CryptoManager RT-7xx is tailored for the automotive market offering ISO 26262 and ISO 21434 compliant hardware security. It supports vehicle-to-vehicle and vehicle-to-infrastructure (V2X), advanced driver-assistance systems (ADAS) and infotainment uses.
  • CryptoCell Root of Trust solutions are programmable, FIPS 140-3 certifiable hardware security modules. They are designed to be integrated into Arm TrustZone-based SoCs or FPGAs where power and space are a consideration.

Find out more: See all Rambus Root of Trust IP Solutions »

What should I keep in mind when selecting a Root of Trust IP?

Root of Trust product designs vary greatly in architecture and capabilities. When selecting a Root of Trust solution, it’s important to ask the right questions to ensure the best level of protection for your specific security needs.

Some questions to consider include:

• What is the end use of the chip?
• Who and what are you protecting against?
• What is the risk of a compromised device?
• What certifications are required?

It’s also worth noting that Root of Trust products can be tailored to match an application’s security threat model, use case, industry segment, lifetime, cost, and geography. Some examples of the different criteria that can be selected include the crypto algorithms, security/anti-tamper mechanisms, and provisioning methods used.

Next steps?

If you have any questions about how to select a Root of Trust for your next project, contact us here.

Explore more resources:
– The Ultimate Guide to Secure Silicon: Root of Trust
– Ask the Experts: PUF-based Security
– Implementing State-of-the-Art Digital Protection with Rambus CryptoManager Security IP

Key topics answered in this episode:

• • What is the current threat environment faced by chip and system makers?
  • What is a root of trust and its role in security?
  • What are the advantages of implementing a root of trust in hardware?
  • What’s new in the third-generation CryptoManager Root of Trust?

What is the current threat environment faced by chip and system makers?

Parvez stressed how crucial it is to tackle supply chain vulnerabilities, cybersecurity risks, and regulatory hurdles that manufacturers face. He pointed out that keeping the manufacturing process secure and protecting intellectual property are top priorities. With the security landscape constantly evolving and regulations like the CHIPS and Science Act of 2022 introducing new challenges, manufacturers are dealing with an ever-growing set of threats.

What is a root of trust and its role in security?

Parvez compared Root of Trust to the foundation of a house—it’s the bedrock of security for semiconductor devices. Just like a strong foundation keeps a house standing, a solid Root of Trust ensures secure boot, safeguards cryptographic operations, and protects intellectual property. A hardware Root of Trust acts as a secure vault, storing keys and handling critical cryptographic tasks to keep everything locked down.

What are the advantages of implementing a root of trust in hardware?

Parvez discussed the advantages of implementing root of trust in hardware, including enhanced security, anti-tampering features, and improved performance. He noted that hardware root of trust is embedded into the chip and cannot be tampered with, providing a higher level of security. However, he also mentioned the cost and flexibility limitations of hardware root of trust.

What’s new in the third-generation CryptoManager Root of Trust?

In this third-generation CryptoManager Root of Trust, Parvez emphasized its three-tier architecture, modularity, and compliance with various industry standards. The new features aim to provide customer flexibility, faster time to market, and pre-certification for different security requirements. The three-tier architecture includes the CryptoManager Core, CryptoManager Hub, and the overall CryptoManager Root of Trust, each offering unique features and benefits.

Key Quote

“A hardware root of trust is the foundation or the foundational concept of security for any semiconductor device. It is what its name literally says, “root of trust.” It is basically everything that your complete device security is based on.” – Parvez Shaik

The cybersecurity threat landscape is dynamic and rapidly evolving. Indeed, attackers are constantly finding new ways to exploit critical vulnerabilities across a wide range of applications and devices. Protecting data and devices requires secure processes running on systems and networks.

A Root of Trust is the foundation on which all secure operations of a computing system depend. It contains the keys used for cryptographic functions and enables a system-wide secure boot process. It is inherently trusted and therefore must be secure by design. The most secure implementation of a root of trust is in hardware safeguarding it from malware and non-invasive or invasive tamper attacks. As such, it can be a stand-alone security module or implemented as a security module within a processor or system on chip (SoC).

Chip makers have varying levels of security expertise and desire for integration. For some customers, a fully turnkey hardware Root of Trust would be ideal. Others wish to build their own Root of Trust but would still like to take advantage of the latest state-of-the-art cryptographic accelerators.

To address these varying customer needs, Rambus has introduced a new three-tier architecture in its industry-leading, 3^rd generation CryptoManager Root of Trust security IP solutions, namely the CryptoManager Root of Trust, Hub and Core families. The CryptoManager Security IP offerings deliver progressively higher levels of functional integration and security, enabling customers to choose the level of security features and capabilities best suited to their unique requirements.

CryptoManager Simplified Three-Tier Architecture

At the highest tier of the architecture is the programmable CryptoManager Root of Trust. The CryptoManager RT-6xx v3 Root of Trust is the latest generation of fully programmable FIPS 140-3 compliant hardware security cores offering Quantum Safe security by design for data center and other highly secure applications, including OCP compliant Caliptra Root of Trust for Measurement with secure boot flow. The CryptoManager RT-6xx family protects against a wide range of hardware and software attacks through state-of-the-art side channel attack countermeasures and anti-tamper and security techniques. With Quantum Safe Encryption (QSE), it provides a future-proof hardware security solution to protect the boot flow and data assets today and into the quantum era.

The CryptoManager RT-6xx allows customers to develop secure and trusted applications that run securely within a trusted boundary. Secure applications can be assigned unique roots and keys, allowing independent permissions and access levels. The RT-6xx inherits its flexible cryptographic accelerators from the embedded Rambus CryptoManager Hub CH-6xx which we’ll describe in the next paragraphs.

The second tier of the CryptoManager architecture is the CryptoManager Hub CH-6xx, a flexible and configurable, efficient bundle of cryptographic accelerator cores. The CH-6xx family products are intended for embedding in customer or Rambus Root of Trust security modules.

Every CryptoManager Hub embeds a CryptoManager Core (tier 3 of the architecture), a collection of efficient symmetric crypto accelerators with state-of-the-art DMA. The CryptoManager Hub adds firmware-controlled public key infrastructure comprising of a true random number generator, classic and, optionally, Quantum Safe accelerators.

Featuring a controller-based design with dedicated secure memories, the CryptoManager Hub offers a variety of classic asymmetric cryptographic accelerators including RSA, ECC, SM2, TRNG, KDF (Key Derive), KAS (Key Agreement), as well as Quantum Safe accelerators like ML-DSA, ML-KEM and SLH-DSA. CryptoManager Hub is offered in off-the-shelf configurations, allowing a choice tailored to the needs of the customer’s application.

The CryptoManager Core, available as a standalone product leveraging a Host CPU or embedded in the Hub, bundles symmetric crypto accelerators for AES, SM4, ChaCha20, SHA-2, SHA-3, SHAKE, SM3 and Poly1305 behind a multi-channel DMA interface. Ideal for power and space-sensitive applications like secure MCU, IoT server, gateway and edge devices, these accelerators are the most versatile, complete crypto solutions that offer the best balance of size and performance available on the market.

For automotive applications, Rambus offers the same three-tiered CryptoManager architecture tailored to the needs of automotive customers. CryptoManager RT-7xx v3 Root of Trust family provides all the functionality for fully programmable ISO 26262 ASIL-D process, ASIL-B or ASIL-D safety mechanisms and ISO 21434 compliant hardware security modules. Dedicated CH-7xx/CC-7xx configurations offer automotive ISO 21434 compliance and ISO 26262 ASIL-B or ASIL-D safety mechanisms.

Configurations differ by cryptographic accelerators contained, protection mechanisms required, including DPA and FIA, and third-party security standard compliance. Rambus can optionally offer dedicated certification support packages to its CryptoManager Hub licensees that provide related certification documentation, test scripts, and dedicated support to achieve FIPS 140-3, SESIP, PSA RoT Component, ISO 26262 (ASIL-B or ASIL-D), ISO 21434 (Cybersecurity) certification with your product embedding a CryptoManager.

“At Untether AI, we provide energy-centric AI inference acceleration from the edge to the cloud, supporting any type of neural network model. Our at-memory compute architecture solves the data movement bottleneck, resulting in high-performance, low-latency inference acceleration without sacrificing accuracy,” said Renxin Xia, Vice President of Hardware at Untether AI. “Ensuring the security of our solutions for data-at-rest and data-in-motion is essential. To address this, we need advanced protection and future-proof security measures. The Rambus CryptoManager Security IP solutions offer a comprehensive suite of security features that enable products like ours to meet the stringent security needs while ensuring the reliability and safety of our AI solutions.”

With over 30 years of security industry leadership, Rambus offers the broadest range of state-of-the-art security IP solutions available. Given the flexibility of the three-tiered CryptoManager Root of Trust architecture, it’s never been easier to get the perfect combination of features and integration tailored to the security needs of your application.

What is a PUF?

A PUF, or physically unclonable function, is a hardware-based security feature that uses unique physical characteristics of a semiconductor to create a kind of fingerprint for the chip. These characteristics come from tiny variants in the manufacturing process that can almost not be copied even if the same design is used. This makes PUF technology extremely secure because they are nearly impossible to clone or tampered with.

The main job of a PUF is to generate secure, unique cryptographic keys without needing to store them permanently. Instead, the keys are created on the spot when needed, which makes it much harder for attackers to access or steal them. This is why PUF technology is widely used in applications like device authentication, data encryption, and secure communication.

PUF plus Root of Trust

PUF technology can be the foundation for a Root of Trust. A Root of Trust is a core building block of security. It is a trusted component that ensures all other parts of the system operate securely. By embedding PUF technology into chips, one can ensure that cryptographic keys and the authentication processes are both unique and resistant to cloning or hacking. For example, ICTK’s Via PUF technology directly integrates with a Root of Trust instantiated in hardware. This enables secure device authentication, encryption, and even protection against both today’s threats and emerging ones like cryptographically-capable quantum computers.

What is a Via PUF?

A Via PUF uses passive via structures instantiated in the chip. These passive components are highly resistant to external factors such as noise, aging, and environmental changes which makes Via PUF far more stable and reliable compared to other PUF technologies.

In contrast to PUF technologies that rely on complex error correction mechanisms to ensure stable outputs, a Via PUF minimizes the need for such processes thanks to its robust architecture. ICTK applies advanced techniques to optimize performance further while significantly reducing unnecessary complexity.

Another major strength of Via PUF is that it has been proven in real-world applications. ICTK has manufactured and distributed over 15 million Via PUF based chips, showcasing not only the technological excellence of the solution, but also its reliability in diverse environments.

Via PUF Design Considerations

From an engineering perspective, implementing a Via PUF involves several key considerations that makes the implementation practical and secure. Via PUF offers unique advantages and requires some additional attention:

Process node selection and validation. Via PUF has been successfully implemented and validated on specific process nodes. For these validated nodes, no additional testing is required, making it easy and faster to integrate into products.

Post-processing for enhanced security. Although Via PUF is stable itself, applying additional post-processing mechanisms can help further strengthen security techniques to ensure the PUF outputs meet the highest entropy and the security for cryptographic applications.

Cryptographic design considerations. When implementing Via PUF, it is essential to consider how it will be used in the final applications. For example, determining how the PUF will support cryptographic functions like encryption and the authentication or how many key derivation functions will be needed. It should be planned during the design phase. This ensures the implementation aligns with the security needs of application.

Protection against non-invasive attacks. As cryptographic systems face increasing threats from non-invasive attacks like differential power analysis (DPA), engineers must implement additional countermeasures. While Via PUF itself is highly resistant to invasive attacks, cryptographic algorithms that use the PUF generated key require extra layers of protection.

Why It Matters

The modern threat environment is increasingly alarming, especially with the sheer number of connected devices that play a role in our daily lives. These connected devices, while convenient, can also pose significant risks. For instance, there have been cases where a simple walkie-talkie was turned into a bomb, illustrating that even IoT devices could potentially be weaponized against us. This highlights the critical importance of device authentication and the component verification to ensure every part of a device is trustworthy.

Watch the full video interview below or skip down the page to read the key takeaways.

Expert

BongHo Kang, Chief Technology Officer, ICTK

Key Takeaways

1. 1. PUF Enhances Security
      PUF technology leverages unique physical variations in semiconductor manufacturing to create cryptographic fingerprints, making it nearly impossible to clone or tamper with. It enables the generation of secure cryptographic keys without the need for permanent storage, strengthening device authentication, data encryption, and secure communication.
   2. ICTK Via PUF Stands Out for Stability and Reliability
      Unlike other PUF solutions, the ICTK Via PUF uses passive Via structures, which are highly resistant to noise, aging, and environmental changes. This reduces the need for complex error correction, making it more stable and easier to integrate into various applications, including IoT, cloud security, and mobile networks.
   3. Key Design Considerations for Implementing Via PUF
      Engineers must consider four critical aspects when designing with Via PUF:
      • Process Node Selection: Via PUF is already validated on many specific nodes, simplifying integration.
      • Post-Processing for Security: Techniques like pre-selection and entropy enhancement improve security.
      • Cryptographic Design: Proper planning ensures alignment with encryption and authentication needs.
      • Protection Against Non-Invasive Attacks: Additional countermeasures like power balancing and masking help defend against differential power analysis and other attack vectors.
   4. The Growing Need for Hardware-Based Security
      The increasing threat landscape, including IoT vulnerabilities and supply chain risks, has driven a shift from software-based to hardware-based security. A strong Root of Trust, building on PUF technology, ensures the authenticity and integrity of devices, making them resistant to emerging cyber threats, including quantum computing.
   5. PUF is a Critical Component in the Future of Secure Electronics
      With the rise of connected devices and evolving cyber threats, PUF technology plays a crucial role in securing supply chains, preventing counterfeits, and enabling trusted device authentication. It provides a robust foundation for encryption, authentication, and secure operations in modern digital systems.

Key Quote

“Companies like Rambus have developed some of the most respected silicon IP for Root of Trust globally, setting the standard in the field. Enhancing and maintaining the strengths of this Root of Trust relies on advanced technologies like PUF. PUF technology plays a critical role in creating a chain of trust, allowing a connected device to defend against hacking attempts by securing and storing cryptographic keys or generating keys for secure communication. In this way, PUF technology helps build the strongest possible security architecture.”

The AutoTech Breakthrough Awards, now in a fifth year, is a globally recognized program that honors excellence and innovation in automotive and transportation technology. With thousands of nominations spanning over 15 countries, the awards are a testament to the advancements driving the future of the auto industry. Categories include areas such as Autonomous Driving, Artificial Intelligence, Electric Vehicles, Automotive Cybersecurity, and more. Rambus winning in the Automotive Cybersecurity category reflects the company’s success in addressing one of the most critical challenges in the automotive world today: ensuring the safety and security of modern vehicles against increasingly sophisticated cyber threats.

Specifically recognized in this year’s AutoTech Breakthrough Award is the RT-64x Root of Trust family of hardware security IP cores providing embedded Hardware Security Module (HSM) functionality for automotive applications. These fully programmable, ISO 26262 ASIL-B and ASIL-D cores, complying with ISO 21434, provide “security by design,” safeguarding against various types of hardware and software attacks. The RT-64x cores protect automotive systems from faults, tampering, and other cyber threats through a multi-layered security architecture. They create a secure foundation for the automotive supply chain, and support multi-tenant deployments enabling secure applications to have unique keys and independent access permissions, ensuring that data and functionality remain compartmentalized and secure.

Rambus is also looking to the future of cybersecurity with our Quantum Safe Cryptography capabilities. As quantum computing becomes more advanced, the threat to current encryption methods grows. Rambus solutions are designed to offer resilience against the future capabilities of quantum computers, ensuring that automotive systems remain secure in the quantum era.

Winning the “Automotive Cybersecurity Innovation Of The Year” award at the 2024 AutoTech Breakthrough Awards is not just a milestone for Rambus; it is a testament to the company’s forward-thinking approach and leadership in automotive cybersecurity. As vehicles become more complex and connected, Rambus continues to deliver the solutions that the industry needs to stay ahead of ever-evolving cyber threats. With its focus on multi-layered security, quantum-safe cryptography, and robust hardware security, we’re  paving the way for a safer, more secure automotive future.

By successfully completing this rigorous certification for the RT-660, we demonstrate, once again, our unwavering commitment to providing top-tier IP that has been meticulously tested and certified by independent labs to meet the highest security benchmarks.

The RT-660 is a silicon-proven Root of Trust that protects against a wide range of hardware and software attacks through state-of-the-art side channel attack countermeasures and anti-tamper security techniques.  Cryptographic accelerators supported by the RT-660 include AES, HMAC, SHA-2/3, RSA, ECC, and our NIST SP800-90A/B certified TRNG.

By deploying the Rambus FIPS 140-3 certified Root of Trust IP, chip and system designers can better navigate the CMVP certification process, significantly reducing time to market when targeting a FIPS 140-3 certificate for their end products.

The Rambus product offering includes the RT-660 hardware IP package, the RT-660 software development kit package, along with a FIPS 140-3 support package that customers can use in their FIPS certification process.

Find out more about the RT-660 Root of Trust IP here.

The discussion focused on the challenges of securing AI systems, drawing parallels with FPGA systems. The discussion focuses on the immense value that an AI inference model holds and how hardware-level security solutions are key to protecting it from potential adversaries.

The discussion also touched on the emerging threat of quantum computers, which could compromise public key cryptography. To counter these threats, Rambus offers a broad portfolio of security IP to protect AI silicon.

The interview concluded with a rather meta discussion on the potential of AI being used to attack AI systems, highlighting further the need for robust security measures.

Expert

• Scott Best, Senior Director of Security Products, Rambus

Key Takeaways

1. Securing Inference Models: Securing AI systems revolves around the protection of the inference model, which holds all the information the AI model was trained against. This model can be a potential target for adversaries or competitors, making it crucial to secure it whether it’s sitting in memory (data at rest) or being pulled into a chip (data in use).
2. Hardware-Based AI Security: AI security needs to take place at the hardware level, and it’s up to chip manufacturers to implement a secure solution. This means securing data privacy and authenticity and making sure that these security measures do not hinder the system’s performance.
3. Quantum Threats to Security: The advent of powerful quantum computers poses a threat to current public key cryptography. Systems being built today that are expected to be in the field for 5-10 years or more need to consider implementing quantum safe cryptography to ensure the privacy and authenticity of their data.
4. Rambus Security IP: Rambus offers a broad portfolio of security IP that enables hardware-based security for AI silicon, as well as Root of Trust IP for data at rest protection, Inline Memory Encryption IP for data in use protection, and Quantum Safe Cryptography solutions to protect devices and data in the quantum era.
5. AI-Driven Security Attacks: It’s possible that adversaries could potentially use AI to attack AI, particularly in power analysis side channel attacks where AI could be trained to find a small signal within a lot of noise. This highlights the need for robust security measures in AI systems.

Key Quote

In AI systems, there’s an inference model produced by a training system, and that inference model is then loaded into an AI chip, and that AI chip then executes that inference model. These inference models contain years of value to companies who created the training system and associated training data. If you’re an adversary or a competitor that wants to see what the “secret sauce” of a particular company is, then the inference model is of great interest.

Related Content

• Products: Rambus Security IP
• Blog: Post-quantum Cryptography (PQC): New Algorithms for a New Era
• Whitepaper: RT-600 Root of Trust Series: A New Generation of Security Anchored in Hardware