Rambus Technical Session Details

Title: Power Delivery Network Design and Optimization for High-Speed Systems with Si Interposer

Date: Wednesday, February 1, 2017

Time: 9:00 am – 9:45 am

Location: Ballroom A

Speaker: Wendem Beyene, Technical Director, Rambus

As the power supply lowers, designers need to pay closer attention to local bypass capacitor selections to suppress power supply noise and jitter. Although on-chip decaps are used to suppress high-frequency noises, off-chip decaps are often needed to reduce low and mid-frequency noise. The impact of on-package and on-interposer decaps to suppress the mid-frequency noise depends on the design rules of the top layer of the Si interposer. The resistive and capacitive characteristics of Si interposer can determine the effectiveness of the decaps placed on the Si interposer. Thus, careful analysis of interposer and package decaps are required.

Title: Methodology for Reusing the Verification Tests and Efforts Beyond Pre-Silicon Verification

Date: Thursday, February 2, 2017

Time: 3:00 pm – 3:45 pm

Location: Ballroom C

Speakers: Dinesh Malviya, Sr. Manager Engineering, Rambus; Sujith Hiremath, Senior Member of Technical Staff – Verification, Rambus

Functional verification language and methodology has matured and converged to a standard (SystemVerilog and UVM). This trend has improved verification quality and reuse to a significant extent. However, there are many areas where verification reuse is not extended due to environment compatibility. Below are several areas where verification efforts could be leveraged to increase overall efficiency and productivity.

• Post silicon validation test vectors
• Firmware code generation
• DFT macro tests documentation
• Direct reuse in different verification environments

This paper introduces a new verification methodology for converting SystemVerilog test sequences in to language neutral test sequence. This language neutral test sequence is automatically converted to other language and format for addressing above reuses.

Rambus Training Sessions

Title: An 8b ADC for a 56Gbps PAM4 Receiver

Date: Wednesday, February 1, 2017

Time: 9:20 am – 10:00 am

Location: Great America 3

Speakers: Kenneth C. Dyer, Senior Principal Engineer Architect, Rambus; Shankar Tangirala, Principal Design Engineer, Rambus

The industry move to 56 Gbps PAM4 signaling requires a major update to the SerDes IP architecture. At the heart of these new long reach (35+ dB) designs is an analog to digital converter. In this talk, you will learn about the architectural tradeoffs and design considerations that lead to an optimal ADC configuration. The ADC described consists of 32 X 8 bit SAR channels, a sampling network, and mixed-signal calibration system running at 28 GS/s.

Title: ADC-Based Link Architecture for Multilevel Signaling at 56G

Date: Wednesday, February 1, 2017

Time: 10:15 am – 10:55 am

Location: Great America 3

Speakers: Masum Hossain, Senior Principal Engineer, Rambus; Nhat Nguyen, Sr. Director of Engineering, Architecture & Design, Rambus

The talk will start with the motivation, advantages and challenges of ADC-based SerDes IP design for 56 Gbps PAM4 signaling at over 35 dB. While the ADC enables scalable digital equalization, modeling the ADC non-idealities is also critical to capture link performance. This talk will walk through the modeling techniques of key blocks for the ADC-based link and will conclude with architectural choices and performance of ADC based links running at 56 Gbps over 35+ dB channels.
Title: PCI Express PHY and controller integration at Gen4: PLDA’s proven methodology for first-time silicon success

Date: Wednesday, February 1, 2017

Time: 11:05 am – 11:45 am

Location: Great America 3

Speaker: Trupti Gowda, Field Application Engineer, PLDA Inc.

PLDA is an industry leader in PCIe with 20 years of experience providing IP cores. With the introduction of PCIe GEN4, the protocol has become more complex. PLDA provides fully integrated PCIe Controller and PHY solutions using a proven methodology based on its vast experience integrating its controller with 3rd-party PHY, including Rambus SerDes PHYs, to help the customer with silicon success. In this talk we present details on our methodology for Controller and PHY integration and highlight its benefits to the customers.

Title: Design and Modelling of 2.5D HBM2 Interposer System

Date: Wednesday, February 1, 2017

Time: 2:00 pm – 2:40 pm

Location: Great America 3

Speaker: Yuri Tretiakov, Principal Engineer, Systems / IC Package Design, Rambus
The HBM2 DRAM interface requires both silicon interposer and a package. Interposer design rules and signal routing floorplan need to be carefully chosen using EM simulations and channel analysis. Lossy silicon substrate and slotted ground effects need to be taken into account. In addition, package design needs to be carefully done, especially from minimizing inductance for most critical power supplies point of view. Also, for most critical power supplies on-package decaps need to be properly selected and placed on a package. This talk addresses how these HBM interposer and package design challenges are met for a HBM2 system operating at 2.0Gbps.

Title: SI and PI Challenges of a 2.5D HBM2 Interposer System

Date: Wednesday, February 1, 2017

Time: 2:50 pm – 3:30 pm

Location: Great America 3

Speakers: Ravi Kollipara, Technical Director, Engineering, Rambus; Joohee Kim, Senior Member of Technical Staff II, Rambus

The HBM2 DRAM interface operates at a max data rate of 2.0 Gbps. The silicon interposer channel is highly resistive and hence, RC limited. The HBM2 interface has more than 1600 switching signals which draw power through the TSVs of the silicon interposer and the vias of the BGA package. Hence, the potential exists for significant SSN which can result in eye closure. In addition, the HBM2 DRAM input mask is more stringent than that of the DDR4 DRAM. This talk addresses how these SI and PI challenges are met for a HBM2 system designed to operate at 2.0 Gbps.

Title: HBM2 Controller and PHY Integration

Date: Wednesday, February 1, 2017

Time: 3:45 pm – 4:25 pm

Location: Great America 3

Speaker: Brian Daellenbach, President, Northwest Logic.

The HBM2 DRAM interface operates at a max data rate of 2.0 Gbps. The silicon interposer channel is highly resistive and hence, RC limited. The HBM2 interface has more than 1600 switching signals which draw power through the TSVs of the silicon interposer and the vias of the BGA package. Hence, the potential exists for significant SSN which can result in eye closure. In addition, the HBM2 DRAM input mask is more stringent than that of the DDR4 DRAM. This talk addresses how these SI and PI challenges are met for a HBM2 system designed to operate at 2.0 Gbps.

According to Russell McCullagh, managing director at Rambus Ecebs, the comprehensive solution utilizes existing ITSO transport infrastructure and current mobile technology to provide a frictionless travel experience for passengers.

“Most people today do not leave home without their smartphone. The devices are practically indispensable as they are used for voice calls, emails, navigation, online shopping and in-store mobile payments,” he told Rambus Press. “Our HCE mobile ticketing solution offers the same ‘shopper friendly’ convenience consumers have come to expect from their smartphones in a transport environment, as it effectively replaces a physical smart card with a secure digital travel wallet.”

Passengers with near field communication (NFC)-enabled smartphones can choose, purchase and download smart travel tickets onto their devices with the Rambus Ecebs HCE Ticketing app. The smartphone can then be used in the same way as a traditional smart card when passing through a station entry barrier – the device is waved or tapped against the station gate, the virtual ticket is validated and the gate opens.

As McCullagh notes, the Rambus Ecebs HCE mobile ticketing solution also saves transport operators significant costs by reducing the need for physical tickets while leveraging pre-existing infrastructure.

“The Rambus Ecebs HCE ticketing solution features an HCE Ticket Wallet Service that utilizes Rambus Ecebs technology as well as Rambus Bell ID’s HCE cloud-based payments platform,” he continued. “The HCE Ticket Wallet Service enables the issuance, key management and lifecycle management of a virtual smart card and ticket wallet stored on NFC smartphones.”

Additionally, says McCullagh, a new HCE Ticketing App is available and has been integrated with the Rambus Ecebs’ suite of smart ticketing products. The ticketing app features a flexible interface with a complete set of APIs to support seamless integration with third-party transport systems – and can also be provided as a white label application.

Future plans for the Rambus Ecebs HCE ticketing app include additional value-added services, such as account-based ticketing, integrated journey planning, real-time updates and third-party offers.

Interested in learning more about Rambus Ecebs HCE mobile ticketing solution? You can check out our product page here and our eBook on the subject here.

“Nearly a half-century ago [in 2001: A Space Odyssey], Arthur C. Clarke and Stanley Kubrick introduced us to cinema’s most compelling example of artificial intelligence: the HAL 9000, a heuristically programmed algorithmic computer,” writes Stork. “The sentient HAL was not only capable of understanding his human colleagues – he could also speak, see, plan, understand emotion and play chess.”

Despite numerous attempts by other science fiction filmmakers, says Stork, HAL remains the most compelling portrayal of machine intelligence in cinema.

“When as a young boy I first saw 2001 (in large-screen Cinerama), I was entranced. That experience, and my many dozens of subsequent viewings, helped lead me to a career in pattern recognition, machine learning, smart sensing, and other technologies that would make a real HAL,” he explains. “I even published a book, HAL’s Legacy: 2001’s Computer as Dream and Reality (MIT Press), and co-created and hosted a PBS documentary on HAL, 2001: HAL’s Legacy, to share my enthusiasm for the masterpiece film and its leading character.”

As Stork notes, since the film’s 1968 debut, humankind has landed on the moon, explored Mars with rovers and even sent robotic probes to study the outer solar systems.

“[However], in contrast to space travel, the development of artificial intelligence (AI) has progressed at a somewhat slower pace,” he continues. “To be sure, the creation of artificial systems that can see, speak, understand language, lip-read, appreciate art, understand emotions and plan is currently one of the greatest challenges facing scientists. We humans are so adept at these tasks we take our expertise for granted; it is when we try to build systems to perform these tasks do we fully appreciate the magnitude of the challenges.”

Nevertheless, says Stork, AI scientists working in pattern and speech recognition, computer vision and machine learning have made significant progress in recent years. This includes deep learning, in which large ‘brain-like’ networks programmed with hundreds of millions of examples are trained to recognize objects, actions and simple descriptions of scenes. In some applications, such networks even outperform human experts.

“One recent example of deep learning is AlphaGo, a computer program developed to play Go, an abstract strategy board game invented in China more than 2,500 years ago,” states Stork. “The advent of AlphaGo, which successfully defeated a professional Go player, illustrates the steady evolution of artificial intelligence.”

Indeed, during the early years of AI, the ultimate benchmark of an advanced computer program was its ability to beat a human opponent at the game of chess by analyzing potential player moves with massive search capabilities. However, this technique is insufficient for Go, which Google defines as a game of “profound complexity,” as there are more possible positions on the Go board than there are atoms in the universe.

“Consequently, AlphaGo is based on AI methods and pattern recognition, using deep neural networks to ‘see’ and ‘understand’ the board position and mimic expert players and further improve the program by learning from games played against itself,” Stork explains. “Put simply, DeepMind focuses on patterns and structure, which, unlike massive search algorithms, seems to be the true foundation of much of human intelligence and advanced artificial intelligence.”

Perhaps not surprisingly, says Stork, artificial intelligence researchers have always found themselves challenged by a perpetually receding goalpost.

“Every time an advance has been made (in speech recognition, planning, image understanding, and so forth) scholars and the public alike say, ‘Oh that’s not true AI… We’ll have AI when…’ Nonetheless, AI researchers have made real progress in recent decades. And now, on HAL’s birthday, we can confidently look back and say HAL has matured considerably since the 1968 debut of 2001: A Space Odyssey,” he concludes.

Image Credit: CES

This demonstration showcased Rambus and Qualcomm Technologies’ efforts on a unique use case highlighting a smart city application. The demo featured both companies’ technologies, illustrating how their combined solutions can provide a more robust and secure IoT end point compared to similar offerings without such solutions. The Qualcomm® Snapdragon^TM 820 processor and the QCA4010 Wi-Fi chip were connected to an IoT cloud service using a protected link while Rambus’ CryptoManager security platform was utilized to illustrate how IoT devices can be safeguarded to significantly reduce service vulnerability to Distributed Denial of Service (DDoS) attacks.

With Qualcomm Technologies’ historic success in embedded hardware processors and Rambus’ success in security-oriented technology, the demo further showcased the combined elements help develop next-generation IoT security features for smart city applications. The CES demo highlighted Rambus’ superior security-focused features which include mutual authentication and encrypted communication embedded into select processors from Qualcomm Technologies. These unique features protect IoT devices from being used by hackers in malicious botnets and prevents the IoT cloud service from being attacked by cloned devices.

As more and more “things” connect to the Internet, the danger of nefarious attackers exploiting unsecured devices looms ever larger. Indeed, DDoS flooding attacks – which seek to disrupt legitimate access to online services – have been deemed “one of the biggest concerns” for cyber security professionals.

Protecting Internet infrastructure companies and services from DDoS attacks can be quite challenging, as it is often difficult to shield the IP layer from a concerted cyber offensive. However, it is important to note that the impact of DDoS attacks can be significantly mitigated by safeguarding vulnerable IoT endpoints. Put simply, protected IoT endpoints act as a critical bulwark against nefarious botnets that exploit and recruit hundreds of thousands of defenseless “zombie” devices.

For instance, an attacker cannot add a device to a botnet without establishing an unauthorized communication channel. Allowing only legitimate, verified cloud services to communicate with IoT devices will help prevent the creation of such rogue channels. This paradigm, facilitated by a hardware root-of-trust, ensures that each IoT device is uniquely and cryptographically verified to determine if it is authorized to connect to a specific service. Infected and hijacked devices that are not authenticated are denied access to the service – reducing the overall effectiveness (and damage) of a DDoS attack on a provider and other services.

It should be noted that an embedded hardware root-of-trust can also be used to help minimize vulnerabilities discovered in IoT products after deployment by providing a secure device management framework to push over-the-air (OTA) patches and firmware updates.

Interested in learning more about IoT security? You can check out our CryptoManager platform product page here, our article archive on the subject here and our white paper here.

##

Qualcomm and Snapdragon are trademarks of Qualcomm Incorporated, registered in the United States and other countries.

Qualcomm Snapdragon and QCA4010 are products of Qualcomm Technologies, Inc.

Rambus, along with the above-mentioned partners, are joining Synopsys, Cadence, INVECAS, VeriSilicon, CEA Leti, Dreamchip and Encore Semi to provide a suite of services that will enable GLOBALFOUNDRIES customers to rapidly implement 22FDX® system-on-chip (SoC) designs in low-power applications spanning Internet-of-Things (IoT), mobile, RF connectivity and networking markets.

According to GLOBALFOUNDRIES, the FDXcelerator Partner Program builds upon the company’s 22nm and 12nm FDX technologies, an alternative to FinFET-based technologies for chips that require performance on demand and energy efficiency at the lowest solution cost.

“GLOBALFOUNDRIES’ 22FDX platform provides a lower-cost migration path from bulk nodes such as 40nm and 28nm, which allows customers to design differentiated, intelligent, and fully-integrated system solutions,” the company explained in a press release. “FDXcelerator partners play a critical role by providing a set of specific solutions and resources that help increase design productivity on FDX technology and reduce time-to-market for its customers. GLOBALFOUNDRIES works closely with program partners to help customers create high-performance 22FDX designs while minimizing development costs through access to a broad set of quality offerings, specific to 22FDX technology.”

Indeed, the partner ecosystem allows GLOBALFOUNDRIES to accelerate its traction in the market and more effectively offer its FDX products and services to a broader range of customers. Moreover, the partner program extends the reach of the FD-SOI ecosystem, creating an open framework that allows selected partners to integrate their products or services into a validated, plug-and-play catalog of design solutions.

Commenting on the above, Dr. Martin Scott, General Manager of the Rambus Security Division, stated that Rambus was pleased to be part of the FDXcelerator program and looked forward to broaden its collaboration with GLOBALFOUNDRIES.

“Through our participation in this program, our DPA-resistant security cores will be made available as part of the pre-validated ecosystem of 22FDX IP. This program helps extend the reach of our best-in-class security cores and accelerates the time-to-market for our customers,” he added.

Interested in learning more? You can check out the GLOBALFOUNDRIES press release here and our DPA-resistant security core product page here.

“Cyber-threats and attacks are becoming increasingly sophisticated and pervasive. Thales products are designed to help organizations stay ahead of the security game by protecting sensitive information from compromise,” said Cindy Provin, chief strategy and marketing officer at Thales e-Security. “By adding Rambus DPA countermeasures, we are able to protect against side-channel attacks, which adds an important element in our robust data security solutions.”

Dr. Martin Scott, senior VP and general manager of the Security Division at Rambus, expressed similar sentiments.

“Thales recognizes the various threats posed by side-channel attacks and has developed solutions that help their customers in businesses, governments and technology sectors mitigate the growing risk associated with these types of attacks,” Scott explained. “Strong countermeasures against these attacks provide the security needed to protect sensitive data and make sure attacks are thwarted.”

As we’ve previously discussed on Rambus Press, Differential Power Analysis is a form of side-channel attack that monitors variations in the electrical power consumption or electro-magnetic emissions of a target device. The basic method involves partitioning a set of traces into subsets, then subsequently computing the difference of the averages of these subsets. Given enough traces, extremely minute correlations can be isolated—no matter how much noise is present in the measurements.

Image Credit: Rambus Security Division (via “Introduction to Differential Power Analysis”)

A typical DPA attack comprises 6 primary stages: communicating with a target device; recording power traces while the target device performs cryptographic operations; signal processing to remove errors and reduce noise; prediction and selection function generation to prepare and define for analysis; as well as computing the averages of input trace subsets and evaluating DPA test results to determine the most probable key guesses. Additional DPA variants include reverse engineering unknown S-boxes and algorithms, correlation power analysis (CPA), probability distribution analysis, high-order DPA and template attacks.

Specific DPA countermeasure techniques include decreasing the signal-to-noise ratio of the power side channel by reducing leakage (signal) or increasing noise, for example, by making the amount of power consumed less contingent upon data values and/or operation (balancing); introducing amplitude and temporal noise; incorporating randomness with blinding and masking by randomly altering the representation of secret parameters and implementing protocol-level countermeasures by continually refreshing and updating cryptographic protocols used by a device.

It should be noted that Rambus has licensed a range of DPA countermeasures to a number of prominent corporations such as Boeing, NVIDIA, Idaho Scientific, The Athena Group, NAGRA and Winbond.

As Woo notes, Moore’s Law, which helped fuel a relentless progression in computing performance, has been an important semiconductor industry mainstay for decades. However, Moore’s Law is waning, with an end on the horizon due to a combination of physical limitations and economic factors.

“With the loss of Dennard Scaling roughly 10 years ago, the industry is at a critical juncture as it contemplates a future in which the two historical driving forces behind semiconductor development and design are no longer present,” he explained. “As advances in process technology slow, increased attention is being paid to emerging computing paradigms and alternative system architectures to drive future performance improvements.”

For example, says Woo, researchers at Supercomputing 2016 (SC16) in Salt Lake City spent time discussing key trends and new approaches to enable the next wave of innovation in computer architecture.

“In this context, the first International Workshop on Post-Moore Era Supercomputing (PMES) convened at the conference and explored potential methods of advancing semiconductor design in a post-transistor scaling world,” Woo continued. “As part of the workshop, Tom Conte detailed the IEEE’s Rebooting Computing Initiative and the International Roadmap for Devices and Systems.”

In addition, Franck Cappello, Kazutomo Yoshii, Hal Finkel and Jason Cong presented a paper that discussed FPGA-powered true co-design flow for high-performance computing in the post-Moore’s Law era.

“Multicore scaling will end soon because of practical power limits. Dark silicon is becoming a major issue even more than the end of Moore’s Law. In the post-Moore era, the energy efficiency of computing will be a major concern. FPGAs could be a key to maximizing the energy efficiency,” the researchers wrote. “FPGAs are gaining the spotlight as a computing resource; modern FPGAs include thousands of hard DSPs or floating-point units. In the preparatory stages, we addressed the technology gaps in adopting FPGA technology for HPC. Our goal is to design and implement ‘Re-form,’ an FPGA-powered true co-design flow that significantly improves the energy efficiency of the post-Moore era supercomputers.”

Field-programmable gate arrays were also the topic of a paper presented by Hiroka Ihara and Kenjiro Taura of the University of Tokyo, who explored the use of the silicon in future HPC scenarios.

“It is known that intermediate fabrics for FPGA accelerators can improve the end-user productivity through both program deployment free of logic synthesis and high portability,” Ihara and Taura stated. “[We discuss] one possible ecosystem for intermediate fab, where pipelined reconfigurable architecture is employed to enable scalable and parallel execution. Such [an] ecosystem can improve the utilization rate of FPGA accelerators in the field of supercomputing.”

According to Woo, the continued evolution of HPC (alongside conventional computing) will require system designers to rethink traditional architectures and software, while considering the use of new devices and materials.

“As the above papers and Microsoft’s Project Catapult illustrate, FPGAs are already helping the semiconductor industry shape the computing platforms of the future. As we prepare for the Post-Moore Era, system architectures will need to evolve to move forward. Traditional processors coupled with FPGAs, along with technologies to minimize data movement, offer new approaches to improving performance and power efficiency and offer a glimpse of things to come in next-gen systems,” he concluded.

“Smart cities encompass all manner of usage models and equipment — parking meters, traffic lights, power and water meters, mobile telephone networks, apps on every resident user’s handheld phone, including cameras and microphones,” she explained. “The engineer’s challenge is integrating all of these devices using common communication links, ubiquitous GPS technology, algorithms that make sense of the data collected and central repositories for relevant data.”

Another issue identified by Morrison is the challenge of maintaining individual privacy in ultra-connected smart cities, a concern that is driving demand for lensless optical sensors such as Rambus’ lensless smart sensor (LSS) technology. Rather than producing images with the kind of visual acuity of a camera, lensless smart sensors generate data and rough images.

“This is a new kind of optic that is extremely flat and easier to use. So instead of generating an image with a photo-sensitive array and a lens, which is what you find in a camera, this replaces the lens with a diffractive grating,” Patrick Gill, principal scientist for Rambus Labs, told Semiconductor Engineering. “You can still see people moving and tell whether they’re sitting, walking, avoiding certain regions and identify a change in the traffic flow or pick up moving car headlights. But it also allows you to replace something that’s analog with a binary diffraction grating. In addition, it’s easy to manufacture—you can do this as large as 2 microns—and it’s a very good detector of motion.”

According to Gill, there can be a wide space between lensless smart sensors, with at least a 140-degree field of view.

“This provides more detail than a motion detector, but also combines an element of privacy so you’re not going to see something end up on YouTube that you don’t want to be made public,” he stated.

One potential deployment for lensless smart sensors, says Gill, is to place the technology on a multi-function chip that measures temperature and humidity – where it’s too expensive to integrate a lens.

“What’s noteworthy is that all camera modules do not survive a solder re-flow,” he added. “The lens would come out as a puddle. But you can make a diffraction grating with a high-temperature polymer. And there are few things that can do this using low power.”

Interested in learning more about smart cities and sensors? The full text of “Smart Cities, Challenging Issues,” by Gale Morrison is available on Semiconductor Engineering here. You can also check out our LSS product page here and our article archive on the subject here.

Perhaps the most important of these principles, says Ashkenazi, is the concept of implementing security at the design phase, with the DHS recommending the use of hardware that incorporates security features to strengthen the protection and integrity of a device. This includes leveraging computer chips that integrate security at the transistor level – embedded in the processor itself – to provide encryption and anonymity.

“Treating security as a primary design parameter rather than a tertiary afterthought is certainly an approach that is long overdue for a very vulnerable Internet of Things,” he explained. “As more and more ‘things’ connect to the Internet, the danger of nefarious attackers exploiting unsecured devices looms ever larger.”

As Ashkenazi points out, building hardware that incorporates hardened security features would see devices protected throughout their lifecycle from chip manufacture, to day-to-day deployment, to decommissioning.

“This can be accomplished with a silicon-based hardware root-of-trust that offers a range of robust security options for IoT devices, including secure connectivity between the IoT device and its cloud service,” he stated.

In addition to implementing security at the design phase, says Ashkenazi, the DHS recommends device manufacturers promote security updates and vulnerability management. Indeed, vulnerabilities may be discovered in products after they have been deployed, even when security is included at the design stage. Such flaws can be mitigated through patching, security updates and vulnerability management strategies.

“From Rambus’ perspective, over-the-air updates and vulnerability management are crucial elements of IoT security. However, to be truly secure, both must be tied to a hardware root-of-trust,” he emphasized. “Infected, hijacked or spoofed devices that are not authenticated are denied access to the service. This approach can also help mitigate the effectiveness (and damage) of DDoS attacks against service providers.”

As Ashkenazi concludes, the six “Strategic Principles” outlined by the DHS will go a long way in helping to convince the industry that IoT devices should not be pushed to market with little regard for security.

“Put simply, IoT security needs to be treated as a primary design consideration, rather than a haphazard afterthought,” he added.

Interested in learning more about IoT security? You can check out our article archive on the subject here.

“[This will] optimize energy provision, temperature control, digital wayfinding (using sensors to find deskspace and map surroundings) and, ultimately, deliver a better overall user experience,” wrote Carrol. “[Moreover], the next generation of building management systems (BMS) will function like the building’s operating system, taking in data and making decisions on how to optimize the building’s design and performance.”

In addition, smart building systems will generate, analyze and interpret vast streams of information. This will allow next-gen smart buildings to marry usage data with information about individual staff movements and work habits to help facilitate collaboration between employees.

“By 2030, we predict that the tactical and operational management of workplaces will largely be undertaken by algorithms analyzing millions of data sets,” he stated. “Buildings will be able to link location data with information from corporate databases and social media to engineer interactions between staff members. Offices will soon become part of the management team of any business – for example, notifying one employee working on a project that another specialist is nearby and suggesting a meeting.”

It should be noted that a recent white paper authored by U.S. furniture giant Haworth expressed similar sentiments, as it described how sophisticated sensors deployed in the workplace of the future can help contribute to employee well-being and increased productivity. These smart sensors will be tasked with constantly monitoring environmental conditions as well as the way employee spaces are used. This will enable workspaces to “shape-shift” for maximum efficiency, automatically altering temperature and lighting levels.

“This is an amazing shift in design thinking,” Haworth’s research program manager Mike Bahr elaborated in a statement quoted by Dezeen Magazine. “[We] believe new technologies can make work better by helping people be their best and soon we’ll see employees drawn to the office in their search for increased wellbeing, engagement, and effectiveness. Why? Because their workspace responds to how they work best.”

To be sure, Haworth envisions a workplace of the future where sensor information detailing light intensity and spectrum, sound amplitude and direction, air quality, odor and occupant location and activity are all integrated – feeding critical data to automatic and responsive environmental systems.

“Occupancy sensors that monitor how employees are using a space are already available and give designers the information to create more effective interior layouts. In [the] future they could generate data for a computer system that adapts a space automatically,” Dezeen Magazine explained. “For example, a meeting room might work better as a less formal area without a central boardroom-style table one day, and a video-conference space the next. New advances in sensors that monitor environmental factors like the intensity of light, sound and air quality are also turning these into key tools for better workspaces.”

As we’ve previously discussed on Rambus Press, this is precisely why lensless smart sensors (LSS) are designed to “understand” the movement, presence and patterns of smart office occupants. Indeed, the presence of an individual, the number of occupants and relevant activity are all passively detected with LSS technology.

So, how do Rambus lensless smart sensors work? Well, LSS offers a novel approach to sensing by combining ultra-small diffractive gratings with standard image sensors. Simply put, light passing through the diffractive grating is intelligently spread onto the image sensor below to form an unrecognizable, yet information-rich blob containing the relevant data from a specific scene. This information is combined with application-specific algorithms that can either visually reconstruct a scene, or extract pertinent data, such as the number and location of occupants.

The resulting data is then analyzed – automatically triggering specific systems and functions within a smart building, such as security, heating, cooling and lighting. This smart approach increases the comfort and safety level of the occupants while significantly reducing energy costs. By rethinking the way digital systems ‘see,’ LSS creates an intelligent infrastructure capable of adapting to the ever-changing needs of the individual in the workplace of the future.

With optics approximately the size of a human hair and a power envelope so low that certain applications could run on energy harvested from their environment, Rambus LSS technology offers the potential to positively disrupt the future of smart buildings and cities, as well as wearables, medical equipment, transportation and manufacturing.

Interested in learning more about Rambus lensless smart sensors? You can check out our LSS product page here.