Counterfeit semiconductors are everywhere. Industry estimates are up to 5% of military and medical equipment contain counterfeit parts. The issue isn’t unique to any particular application or geography. In 2017’s “Operation Wafer,” the European-wide Joint Customs Operation (JCO) seized more than one million counterfeit semiconductor devices during a 2-week operation. One million devices – in just two weeks! Industry Week has pegged the fake semiconductor market at $75B, with Havocscope reporting more than $169B in counterfeit parts circulating in the marketplace. The problem is so prevalent that the Global Semiconductor Alliance started a working group on supply chain security.

So…why should fake chips matter to you? Lets talk safety. There is no way to understand how counterfeit parts function. Are they actually doing what the original (authentic) part is supposed to do, or are they operating differently? An even scarier thought, are they intentionally compromising the systems around them? Or are they passing information they gather to an adversary? Confirmed recent incidents of counterfeit parts being found in the field include automated external defibrillators (AED), airport landing lights, intravenous (IV) drip machines, and braking systems for high speed trains. Each of these represent a significant risk to human health and safety.

Device OEMs are forced to address a key question, “if we can’t trust the authenticity of semiconductor components we buy, how can we (and our customer) really trust the devices we make?” Frankly, the answer is “we can’t.”

So how can we fix this? Trust starts at the silicon level, but that trust is only as good as the security applied during manufacturing. That’s where the Rambus CryptoManager Infrastructure becomes a highly valuable tool towards guaranteeing semiconductor authenticity, starting at time of initial manufacturing and stretching all the way to end of life.

During the manufacturing of a chip, whether at an OEM or 3rd-party facility, CryptoManager Infrastructure securely provisions (injects) each and every semiconductor with a unique cryptographic key, or other secure data, in a known-secure area of the chip. Each key is unique to the individual chip and forms the basis of a trusted identity. The process is completely automated. There is no human intervention, allowing the process to take place in just about any facility around the world. Keys are securely generated in air-gapped systems, and only known to the OEM. Once the chip leaves the factory and is placed into a device, the authenticity of that chip can be checked at any time using the Rambus Key Management Service (KMS).

Chip OEMs who use our infrastructure product can provide a chip authenticity guarantee to their device OEM customers, who can then provide the same guarantee to their customers. By cutting down the number of counterfeit chips, we lower the risks to safety and security in electronic devices.

As Woo notes, Moore’s Law, which helped fuel a relentless progression in computing performance, has been an important semiconductor industry mainstay for decades. However, Moore’s Law is waning, with an end on the horizon due to a combination of physical limitations and economic factors.

“With the loss of Dennard Scaling roughly 10 years ago, the industry is at a critical juncture as it contemplates a future in which the two historical driving forces behind semiconductor development and design are no longer present,” he explained. “As advances in process technology slow, increased attention is being paid to emerging computing paradigms and alternative system architectures to drive future performance improvements.”

For example, says Woo, researchers at Supercomputing 2016 (SC16) in Salt Lake City spent time discussing key trends and new approaches to enable the next wave of innovation in computer architecture.

“In this context, the first International Workshop on Post-Moore Era Supercomputing (PMES) convened at the conference and explored potential methods of advancing semiconductor design in a post-transistor scaling world,” Woo continued. “As part of the workshop, Tom Conte detailed the IEEE’s Rebooting Computing Initiative and the International Roadmap for Devices and Systems.”

In addition, Franck Cappello, Kazutomo Yoshii, Hal Finkel and Jason Cong presented a paper that discussed FPGA-powered true co-design flow for high-performance computing in the post-Moore’s Law era.

“Multicore scaling will end soon because of practical power limits. Dark silicon is becoming a major issue even more than the end of Moore’s Law. In the post-Moore era, the energy efficiency of computing will be a major concern. FPGAs could be a key to maximizing the energy efficiency,” the researchers wrote. “FPGAs are gaining the spotlight as a computing resource; modern FPGAs include thousands of hard DSPs or floating-point units. In the preparatory stages, we addressed the technology gaps in adopting FPGA technology for HPC. Our goal is to design and implement ‘Re-form,’ an FPGA-powered true co-design flow that significantly improves the energy efficiency of the post-Moore era supercomputers.”

Field-programmable gate arrays were also the topic of a paper presented by Hiroka Ihara and Kenjiro Taura of the University of Tokyo, who explored the use of the silicon in future HPC scenarios.

“It is known that intermediate fabrics for FPGA accelerators can improve the end-user productivity through both program deployment free of logic synthesis and high portability,” Ihara and Taura stated. “[We discuss] one possible ecosystem for intermediate fab, where pipelined reconfigurable architecture is employed to enable scalable and parallel execution. Such [an] ecosystem can improve the utilization rate of FPGA accelerators in the field of supercomputing.”

According to Woo, the continued evolution of HPC (alongside conventional computing) will require system designers to rethink traditional architectures and software, while considering the use of new devices and materials.

“As the above papers and Microsoft’s Project Catapult illustrate, FPGAs are already helping the semiconductor industry shape the computing platforms of the future. As we prepare for the Post-Moore Era, system architectures will need to evolve to move forward. Traditional processors coupled with FPGAs, along with technologies to minimize data movement, offer new approaches to improving performance and power efficiency and offer a glimpse of things to come in next-gen systems,” he concluded.

“Drones, also known as UAVs (unmanned aerial vehicles) and UASs (unmanned aerial systems), need a variety of internal components to work effectively. The list includes MEMS (such as accelerometers, gyroscopes, magnetometers and pressure sensors), GPS modules, processors and digital radios,” he explained.

“Together, these components tell a drone where to go, how to orient itself and how to avoid collisions, among other things. Yet many of these same components can also be exploited to wrest control away from a drone’s authorized operator or onboard navigation system.”

Indeed, as Oleg Petrovsky, a senior research engineer at HP Enterprise Security Services points out, drones are typically packed with a wide variety of hardware modules, along with supporting software and firmware used for various configurations.

“Overall, each UAS has to have a flight controller, a receiver, electronic speed controllers, motors and, perhaps, a telemetry module,” he told SemiEngineering. “Each could be vulnerable to a number of physical and electronic type of attacks.”

Perhaps not surprisingly, Petrovsky has identified multiple security vulnerabilities, including using Mission Planner to capture, modify and insert a data stream into a telemetry link connection over a serial port. Another attack conducted by the security researcher involved spoofing the ground station link to assume full control of the interface. Telemetry feeds, says Petrovsky, can be transmitted via Wi-Fi, Bluetooth, ZigBee or a proprietary radio connection.

“Using telemetry and command feed attack methods, a malicious actor can, for instance, upload an arbitrary flight path to the drone,” he added.

According to Asaf Ashkenazi, a senior product management director in Rambus’ security division, drone threats are likely to increase unless effective security protocols are implemented.

“You will see more and more connected drones, or drones that are connected to a device that is connected to the internet,” he told the publication. “And once you have this link, you can attack the drones from anywhere in the world.”

Many semiconductor vendors, says Ashkenazi, are serious about adding security mechanisms to their silicon.

“To enable a security system, you can’t have just the silicon manufacturer involved. There needs to be collaboration with the drone manufacturers and the drone manufacturers have to have motivation to add security,” he concluded.

Interested in learning more? “Making Drones Secure” can be read on Semiconductor Engineering here.

A number of prominent individuals were invited to speak at the event, including Rambus CMO Jerome Nadel.

Nadel, who has an extensive background in both design and marketing, told forum attendees the two are intertwined and should not be thought of as disparate entities.

“Traditional marketers are primarily concerned with formulating strategy, generating content, increasing traffic, tracking lead generation, quantifying analytics and closely following reporting,” Nadel explained. “Meanwhile, designers are typically focused on emphasizing, defining, ideating, prototyping and testing.”

Rambus’ approach, says Nadel, blends strategy and design, a combination that is particularly important in the evolving semiconductor space where differentiation is a must. As an example, Nadel highlighted Rambus’ lensless smart sensor (LSS) technology, which was developed to help enable the next-generation of low-power sensing for consumers. At one millimeter thin, these thermal and visible light sensors are small enough to integrate directly into existing devices and applications, including digital eyewear, smart homes, VR and AR, as well as automotive.

To develop and explore potential use cases for LSS, Rambus collaborated with design firms IXDS and frog in the context of a Partners-in-Open-Development (POD) program.

“We asked them to prototype a number of minimum viable products around LSS in specific, clearly defined verticals. They helped us open up to a new and different way of thinking, allowing us to achieve a viable strategy critical for a very competitive IoT marketplace,” he continued.

“This successful collaboration illustrates the value of adopting a holistic approach to marketing – one that tactfully blends logic and a long-term marketing strategy with passion and a design-centric, forward-facing consumer mentality.”

At Rambus, says Nadel, this way of thinking has helped accelerate and optimize the branding process for LSS as well as other products in the company’s diverse portfolio.

“Understanding how our customers and partners will use a product plays a direct role in influencing its development,” he concluded.

“It is therefore essential for semiconductor marketing teams to think like designers upstream at the beginning of the creative process, rather than simply focusing on more traditional marketing methods downstream when a product is taped out or finalized. If you are promoting what you helped create, you naturally have a better understanding of the product itself.”

“RISC-V can be used without charge and freely modified, similar to the way open-source programs like Linux are now used by many companies,” Clark explained. “Its backers see it is an antidote to stiff development costs and other market forces that have deterred chip designers.”

As Clark notes, RISC-V isn’t the first attempt at open-source chips.

“[However], backers say it has gained outsize momentum, inspiring programmers to write versions of Linux and other software to exploit it,” he added.

Commenting on the announcement, Rambus CEO Ron Black told the Wall Street Journal that the SiFive idea was quite intriguing.

“If the industry is not going to grow, maybe we should think about different models,” he said.

SiFive CTO Yunsup Lee expressed similar sentiments during an interview with The Platform.

“The semiconductor industry is at an important crossroads,” he stated. “Moore’s Law has ended and the traditional economic model of chip building no longer works. Unless you have tens, if not hundreds, of millions of dollars, it is simply impossible for smaller system designers to get a modern, high performance chip, much less one customized to unique requirements.”

Meanwhile, David Kanter, a processor analyst with The Linley Group, told the EE Times open source hardware could potentially decrease the cost of new design starts by enabling more design re-use and lower IP costs. However, Kanter cautioned that while open source has proven to be a powerful force in the software world, it remains uncertain how the concept will map into the hardware world.

Nevertheless, RISC-V has already gained significant momentum in recent months. For example, engineers at ETH Zurich and the University of Bologna debuted the 32-bit PULPino, an open-source microprocessor based on RISC-V architecture. The PULPino – taped out as a 65nm ASIC – is now available for RTL simulation and FPGA mapping.

On the software side, engineers at Genode unveiled new support for RISC-V CPU architecture. For the uninitiated, the Genode Framework can perhaps best be described as a tool kit for building highly secure special-purpose operating systems. It is capable of scaling from embedded systems with as little as 4 MB of memory to highly dynamic general-purpose workloads. According to Norman Feske of OS News, RISC-V is a “possible answer” to the call for more trustworthy hardware. To be sure, such a prospect is what motivated the Genode project to take a closer look at the open source ISA.

As recently noted in “Charting a New Course for Semiconductors,” the success of open-source software – as opposed to a closed, walled-garden approach – has set an important precedent for the semiconductor industry. In fact, more than 95 percent of today’s web servers run on variants of the Linux operating system, while approximately 85 percent of smartphones sold worldwide use the open-source Android mobile operating system (OS).

Interested in learning more about RISC-V architecture? You can check out the official RISC-V Foundation site here.

“The semiconductor industry is not growing; there has been unparalleled consolidation and money spent on acquisitions, and all of this is coming from the fact that this is a non-growth market,” Rambus CMO Jerome Nadel told The Next Platform. “The industry is only reaping 1.5 percent of the billions in value it creates, so we are asking is what alternative paths exist.”

According to Nadel, one potential alternate route is open source hardware, which could help alleviate the severe margin erosion plaguing the semiconductor industry.

“Investments in the costs and design and fabrication are now so enormous that the notion of ‘build it once and reap the benefit’ is one that is not sustainable as costs go up and margins go so far down,” he explained. “To counter this trend, the only real options lie in custom ASIC and FPGAs, but more broadly in the future of open source hardware.”

As Nadel told The Platform, Rambus joined the RISC-V Foundation earlier this year as a founding member and is backing the open source initiative due to the sheer economics of designing new novel instruction set architectures (ISAs).

“Commercial chip vendors typically pay hefty, multi-million dollar license fees to use proprietary ISAs,” he added. “However, such prices are often too high for academia and many small companies, leading to stifled competition and innovation as well as more expensive chips.”

As we’ve previously discussed on Rambus Press, RISC-V has gained significant momentum over the past year. In April, engineers at ETH Zurich and the University of Bologna debuted the 32-bit PULPino, an open-source microprocessor based on RISC-V architecture. The PULPino – taped out as a 65nm ASIC – is now available for RTL simulation and FPGA mapping. On the software side, engineers at Genode unveiled new support for RISC-V CPU architecture. For the uninitiated, the Genode Framework can perhaps best be described as a tool kit for building highly secure special-purpose operating systems. It is capable of scaling from embedded systems with as little as 4 MB of memory to highly dynamic general-purpose workloads.

As recently noted in “Charting a New Course for Semiconductors,” the success of open-source software – as opposed to a closed, walled-garden approach – has set an important precedent for the semiconductor industry. To be sure, more than 95 percent of today’s web servers run on variants of the Linux operating system, while approximately 85 percent of smartphones sold worldwide use the open source Android mobile operating system (OS).

Interested in learning more about RISC-V architecture? You can check out the official RISC-V Foundation site here.

“[Connectivity adds] many of the features that consumers now expect in mobile devices as well as some new ones that ultimately will lead to autonomous vehicles,” she explained.

“But along with those changes are some nagging questions about just how safe [this] technology will be for consumers and others around them, and whether the whole system can be secured.”

As Mutschler acknowledges, such questions have been asked ever since the introduction of infotainment systems in cars.

“[However], the volume is increasing as more critical systems are connected to in-car networks and as more wireless features are added into vehicles,” she noted. “In effect, every new car is now an IoT device, and like every connected device, there are benefits and risks. But in the case of a two-ton object moving at high speed down a crowded highway, the risks are much more serious.”

According to Simon Blake-Wilson, VP of products and marketing for Rambus’ Cryptography Research Division, the industry is currently struggling with the concept of designing secure vehicles.

“We struggle in the sense that if you think about the security you apply to a mobile phone, it’s not like there is a magic bullet solution for mobile phone security. Similarly, everything about this from an [automotive] perspective must take into account many different security aspects,” Blake-Wilson told Semiconductor Engineering. “[Moreover], we struggle with the idea of whole-vehicle security just in the sense that people often come away expecting a magic bullet that’s going to solve the problem. We see cars being like other Internet connected objects, except much worse.”

As Mutschler points out, silicon foundries are now placing encryption algorithms into silicon with various technologies, including Rambus CryptoManager. Essentially, the CryptoManager platform acts as a foundational component capable of powering multiple security solutions. According to Blake-Wilson, a root of trust is the goal with any hardware-based security technology.

“For example, when you provision over-the-air updates, typically you sign those updates using a cryptographic mechanism called a digital signature scheme, with a private key and a public key. You sign the update with the private key, and the person that checks the signature has to have the right public key to verify it,” he continued. “A hardware root of trust manages the keys that you need to have, securing then in the right place to power the different security solutions. Once the key is in the right place, you go to the next step and use the key to check the signature. In the same way, you could use a hardware root of trust to provision keys and secure communications across the vehicle CAN [controller area network] bus as well.”

Including a root of trust in automotive semiconductors, says Blake-Wilson, will mark a critical security milestone for the industry.

“There will be a number of different applications or services that [require] security [measures]. Putting the right foundational capabilities into the chips that can be used by a variety of different applications will be key,” he concluded.

Interested in learning more about the Rambus CryptoManager platform? You can check out the CryptoManager product page here.

“The driving factors for the growth of this market include increasing demand for advanced SoCs in the consumer sector, increased funding from governments and investors, emerging IoT ecosystem, recovering automotive sector and growing popularity of miniaturized devices,” MarketsandMarkets researchers explained in a recently published report summary.

“[In addition], increasing demand for pervasive M2M (machine-to-machine) connectivity and a rich user experience across industries has spurred new opportunities for growth in both traditional and emerging embedded processor market.”

The researchers also noted that emerging multi-core processors (quad-core and octa-core) for enhanced real-time experience in smart consumer electronics such as smartphones and smart wearables are expected to drive the embedded processor IP market.

“A strong consumer demand for smartphones, tablets, and other mobile devices is fueling significant growth within the semiconductor industry, and the rush to develop differentiated and powerful mobile solutions is driving rapid change within the entire ecosystem,” the researchers added.

“Mobile phones and tablets have become the necessity of every individual which has increased the demand for the same; this is expected to drive the semiconductor IP market. Key players in the market such as Synopsys (U.S.), ARM (U.K.), and Rambus (U.S.) design chips exclusively to cater this application sector because of its growth potential.”

The full report, titled “Semiconductor (Silicon) IP Market by Form Factor (Integrated Circuit IP, SOC IP), Design Architecture (Hard IP, Soft IP), Processor Type (Microprocessor, DSP), Application, Geography and Verification IP – Forecast & Analysis to 2022,” is available for purchase here.

As per the terms of the new three-year agreement, Toshiba will be licensing a wide range of technologies from Rambus to cover products that include SoCs with DRAM memory controllers and/or serial link interfaces, as well as Flash Memory and system products.

“We are pleased to have expanded our relationship with Toshiba, one of the global leaders in the semiconductor industry,” said Luc Seraphin, senior vice president and general manager of the Memory and Interfaces Division at Rambus. “Toshiba has been a valuable customer of Rambus for more than a decade and this renewal reinforces the value of our innovative technology and IP.”

As we’ve previously discussed, Rambus’ Memory and Interfaces Division develops products and services that solve the power, performance, and capacity challenges of the mobile, connected device, and cloud computing markets.

More specifically, Rambus enhanced standards-compatible and custom memory and serial link solutions include chips, architectures, memory and chip-to-chip interfaces, DRAM, IP validation tools, and system and IC design services.

Interested in learning more? You can check out our Memory and Interfaces Division page here.

Thayer professor Eric Fossum, the engineer and physicist who invented the CMOS image sensor used in a plethora of mobile devices, says QIS is targeted at a number of applications and platforms, including security cameras, astronomy and life science imaging.

Image Credit: Robert Gill (Dartmouth Now)

“Light consists of photons, little bullets of light that activate our neurons and make us see light,” Fossum explained. “The photons go into the semiconductor [the sensor chip] and break the chemical bonds between silicon atoms and, when they break the bond, an electron is released. Almost every photon that comes in makes one electron free inside the silicon crystal. The brighter the light, the more electrons are released.”

As Fossum notes, one of the challenges QIS addresses is counting how many electrons are set free by photons. This is particularly important for very low light applications, such as life science microscopy, photography, quantum cryptography and the burgeoning Internet of Things (IoT).

“When we build an image sensor, we build a chip that is also sensitive to these photons. We were able to build a new kind of pixel with a sensitivity so high we could see one electron above all the background noise.”

Indeed, the new pixels are considerably smaller than regular pixels, as they are designed to sense only one photon, although many more are placed on the sensor to capture the same number of total photons from the image.

“We’d like to have 1 billion pixels on the sensor and we’ll still keep the sensor the same size,” said Thayer PhD candidate Jiaju Ma.

According to Fossum, the new pixels are capable of sensing and counting a single electron for the first time – without resorting to extreme measures, such as cooling the sensor to minus 60 C and/or avalanche multiplication.

“Avalanche multiplication may be thought of as an electrically induced chain reaction, but the strong electric fields necessary lead to reliability issues and it is difficult to make small pixels,” he explained. “We deliberately wanted to invent it in way that is almost completely compatible with today’s CMOS image sensor technology so it’s easy for the industry to adopt.”

The question, says Fossum, was how to design QIS in a current, commercially accessible, not-too-expensive CMOS process.

“You use all the tricks you can think of. Being able to measure one electron is fundamental from a scientific point of view and we were able to do it without a ‘Manhattan Project.’ ”

Fossum also confirmed that the image sensor community seemed receptive to the new technology.

“Engineers in industry are continuously improving the state of the art. They have to worry about the next product or the product after the next product,” he continued. “They don’t have the luxury of thinking like, ‘What are we going to do 10 years from now?’ That’s where I’m happier thinking—in that timescale.”

It should be noted that the QIS project is funded by Rambus, where Jiaju Ma has served as an intern over the past two years.

“A company representative offered some extraordinarily high praise for [Ma], calling him a ‘superstar intern,’” Fossum added. “We hope to continue our collaborations with Rambus in the future.”