The US Department of War (DoW) selected BAE Systems to qualify a new generation of integrated circuits using 12nm technology, which will be radiation hardened and available to the space community to address future high-performance requirements.

“Our RH12 Storefront provides a turnkey solution for customers requiring radiation-hardened 12 nanometer integrated circuits,” said Joe Dziezynski, director of Space Systems at BAE Systems. “This approach uses commercial foundry technology for space missions, qualifying not only the library components but also the process for how each of those components are designed into customer integrated circuits. Customers now have a one-stop-shop for state-of-the-art microelectronics performance to complete their missions in the harsh space environment.”

For the RH12 Storefront program, Rambus supplies BAE Systems with solutions from our industry-leading Silicon IP portfolio including DDR4 memory and PCIe controllers. The move to 12nm technology has a pronounced positive impact on the power and performance of space-based systems, and Rambus is proud to support this mission-critical endeavor. BAE Systems offers RH12 integrated circuit development and production services to the industry for use in defense, space, intelligence, research and commercial space missions.

View the BAE Systems press release for more details.

Dynamic Power Management

The demonstration reveals how L0p mode enables dynamic lane scaling without compromising performance. This innovative feature allows systems to adjust the number of active lanes based on actual bandwidth requirements while maintaining consistent data throughput. By switching from x4 to x1 configuration seamlessly, the system achieves significant power savings without the traditional overhead of link renegotiation.

Real-Time Analysis with XpressAGENT

Using the Rambus XpressAGENT debug IP, the demonstration provides a clear comparison between conventional lane width transitions and the new L0p capability. The traditional method shows multiple LTSSM intermediate steps that interrupt traffic flow and require additional software handling. In contrast, L0p transitions occur smoothly without any interruption to data transmission.

Technical Implementation

The demonstration utilizes:

• FPGA Virtex UltraScale+ implementation
• Rambus PCIe 6.x IP
• Seamless integration between rootport and endpoint
• Real-time monitoring and control capabilities

This technical showcase highlights our commitment to advancing PCIe technology while optimizing power consumption for modern computing needs. Watch the full demonstration to see how these innovations can benefit your next-generation designs.

Watch the demonstration video below to see L0p and FLIT mode in action.

The interview highlighted the latest generation of PCI Express, PCIe 7.0. This new generation doubles data rates from 64 to 128 Gigatransfers per second (GT/s), will support optical interconnects, and includes features for data protection.

Rambus has announced a new family of PCI 7.0 IP solutions that includes a PCIe 7.0 Controller, a PCIe 7.0 Switch IP, and a PCIe Retimer IP.

Check out the full video interview below or skip to read the key takeaways.

Expert

• Lou Ternullo, Senior Director of Product Management, Rambus

Key Takeaways

1. AI-Driven PCIe Evolution: The rapid evolution of the PCI Express specification is primarily driven by AI applications, and more specifically generative AI. Industry trends such as the disaggregation of compute storage are also contributing to this evolution.
2. PCI 7.0 Advancements: The seventh generation of the PCI Express specification, PCIe 7.0, doubles the data rate of the previous generation from 64 GT/s to 126 GT/s. It continues to support features from PCIe 6.0, including flip mode and PAM4.
3. Enhanced Data Protection Features: PCI 7.0 brings enhanced data protection features to secure the transmission of data from server CPUs to endpoints. These include Integrity Data Encryption (IDE) and Trusted Execution Environment Device Interface Security Protocol (TDISP).
4. Rambus PCIe 7.0 IP Announcement: Rambus has announced a family of PCI 7.0 Controller IP. This portfolio includes a PCIe 7.0 Controller, host or endpoint, a PCIe 7.0 Switch IP and a PCIe 7.0 Retimer IP.
5. Rambus End-to-End PCIe Solution: Rambus offers a differentiated, end-to-end solution for PCIe systems, backed up by over 20 years of design experience. Rambus also offers XpressAGENT, an embedded debug logic analyzer tool, for rapid link bring up.

Key Quote

The PCI Express specification has evolved rapidly in recent years and the primary application category is AI, more specifically generative AI powered by large languages models (LLMs). In addition, there are also some wider industry trends such as disaggregation that are also influencing developments in the PCIe specification.

Related Content

• Products: Rambus PCIe Controller IP
• News: Rambus Unveils PCIe 7.0 IP Portfolio for High-Performance Data Center and AI SoCs
• Blog: PCIe 7.0: Speed, Flexibility & Efficiency For The AI Era

• PCIe 7.0 Controller designed to deliver the high bandwidth, low latency, and robust performance required for next-generation AI and HPC applications
• PCIe 7.0 Retimer for highly-optimized, low-latency data path for signal regeneration
• PCIe 7.0 Multi-port Switch that is physically aware to support numerous architectures
• XpressAGENT^TM to enable customers to rapidly bring-up first silicon

“The burgeoning landscape of data center chip manufacturers, driven by the emergence of novel data center architectures, necessitates the availability of high-performance interface IP solutions to foster a robust and thriving ecosystem,” said Neeraj Paliwal, SVP & GM of Silicon IP at Rambus. “The Rambus PCIe 7.0 IP portfolio addresses this challenge by delivering unparalleled bandwidth, low latency, and security features. These components work together to provide a seamless, high-performance solution that meets the rigorous demands of AI and HPC applications.”

Rambus PCIe 7.0 Controller IP key features include:

• Supports PCIe 7.0 specification including 128 GT/s data rate
• Implementation of low-latency Forward Error Correction (FEC) for link robustness
• Supports fixed-sized FLITs that enable high-bandwidth efficiency
• Backward compatible to PCIe 6.0, 5.0, 4.0, etc.
• State-of-the-art security with an IDE engine
• Supports AMBA AXI interconnect

Rambus PCIe 7.0 Retimer IP key features include:

• Supports PCIe 7.0 specification x2 to x16 lanes
• Pre-integrated Xpress Agent debug analysis IP
• Highly-configurable equalization algorithms with adaptive behaviors
• Power modes and intelligent clock gating to best manage controller IP

Rambus PCIe 7.0 Switch IP key features include:

• Highly scalable up to 32 ports configurable external or internal endpoints
• Physically aware to account for port placements across large die
• Superior performance through non-blocking architecture
• Allows seamless migration from FPGA prototyping design to ASIC/SoC production design with the same RTL

Rambus PCIe XpressAGENT key features include:

• Non-intrusive, intelligent, in-IP debug/logic analyzer for PCIe Controller, Retimer and Switch IP enabling rapid first-silicon bring-up
• Integrates with any PIPE compliant SerDes
• Provides unified access to PHY, MAC and Link Layers locally or remotely via a CPU-agnostic API
• Provides pre-emptive monitoring and diagnosis via remote access for infield products

In addition to the PCIe IP portfolio, Rambus also offers industry-leading interface IP for HBM, CXL, GDDR, LPDDR, and MIPI. For more information, visit www.rambus.com/interface-ip.

Have you ever thought about the technologies that enable generative AI, including Chat GPT and Google Bard? Semiconductor technologies like DDR5, High-bandwidth Memory (HBM), GDDR, and PCI Express are critical in the training and deployment of generative AI.

Security will be another essential requirement as Generative AI proliferates to the edge and increasingly to client systems and smart end points. Safeguarding AI data and assets will require security anchored in hardware.

Check out the Rambus infographic below, “The Powerful Technologies that Enable Systems like ChatGPT to Thrive” to learn more.

Find out all about PCIe 6.1 in the article below.

Contents

• What is PCIe 6.1?
• What’s new with PCIe 6.1?
• Why PCIe 6.1 now?
• Conclusion

What is PCIe 6.1?

Since PCIe 3, each new generation of the standard has seen a doubling in the data rate. PCIe 6.1 boosts the data rate to 64 gigatransfers per second (GT/s), twice that of PCIe 5.0. For a x16 link, which is typical of graphics and network cards, the bandwidth of the link reaches 128 gigabytes per second (GB/s). As in previous generations, the PCIe 6.1 link is full duplex, so it can deliver that 128 GB/s bandwidth in both directions simultaneously for a total bandwidth capacity of 256 GB/s.

PCIe has proliferated widely beyond servers and PCs, with its economies of scale making it attractive for data-centric applications in IoT, automotive, medical and elsewhere. That being said, the initial deployments of PCIe 6.1 will target applications requiring the highest bandwidth possible and those can be found in the heart of the data center: AI/ML, HPC, networking and cloud graphics.

The following chart shows the evolution of the PCIe specification over time:

What’s new with PCIe 6.1?

To achieve the 64 GT/s, PCIe 6.1 introduces new features and innovations:

1. PAM4 Signaling:

On the electrical layer, PCIe 6.1 uses PAM4 signaling (“Pulse Amplitude Modulation with four levels”) that combines 2 bits per clock cycle for 4 amplitude levels (00, 01, 10, 11) vs. PCIe 5.0, and earlier generations, which used NRZ modulation with 1 bit per clock cycle and two amplitude levels (0, 1).

2. Forward Error Correction (FEC)

There are always tradeoffs, and the transition to PAM4 signal encoding introduces a significantly higher Bit Error Rate (BER) vs. NRZ. This prompted the adoption of a Forward Error Correction (FEC) mechanism to mitigate the higher error rate. Fortunately, the PCIe 6.1 FEC is sufficiently lightweight to have minimal impact on latency. It works in conjunction with strong CRC (Cyclic Redundancy Check) to keep Link Retry probability under 5×10-6.  This new FEC feature targets an added latency under 2ns.

While PAM4 signaling is more susceptible to errors, channel loss is not affected compared to PCIe 5.0 due to the nature of the modulation technique, so the reach of PCIe 6.1 signals on a PCB will be the same as that of a PCIe 5.0.

3. FLIT Mode:

PCIe 6.1 introduces FLIT mode, where packets are organized in Flow Control Units of fixed sizes, as opposed to variable sizes in past PCIe generations. The initial reason for introducing FLIT mode was that error correction requires working with fixed size packets; however, FLIT mode also simplifies data management at the controller level and results in higher bandwidth efficiency, lower latency, and smaller controller footprint. Let’s address bandwidth efficiency for a minute: with fixed-size packets, the framing of packets at the Physical Layer is no longer needed, that’s a 4-byte savings for every packet. FLIT encoding also does away with 128B/130B encoding and DLLP (Data Link Layer Packets) overhead from previous PCIe specifications, resulting in a significantly higher TLP (Transaction Layer Packet) efficiency, especially for smaller packets.

4. Other changes in PCIe 6:

• L0p mode – enabling traffic to run on a reduced number of lanes to save power
• A new PIPE specification – for the PHY to Controller interface

PCIe 6.1 Fun Fact: the x32 and x12 interface widths from earlier generations are dropped. While these widths are available in PCIe 5.0 and earlier specifications, these widths were never implemented in the market.

Why PCIe 6.1 now?

Before 2015, the PCIe specification was well ahead of the market in terms of available bandwidth required for use cases. After 2015, global data traffic has exploded. Data centers transitioned to 100G Ethernet (and up) pushing the bottleneck to the PCIe interconnects in servers and network devices.

The PCIe 6.1 specification fully supports the transition to 800G Ethernet in data centers: 800 gigabit per second (Gb/s) requires 100 GB/s of unidirectional bandwidth which falls within the 128 GB/s envelope of a x16 PCIe 6.1 link; 800G Ethernet, like PCIe, is full duplex. Further, data center general compute and networking are not the sole driving forces behind PCIe 6.1. AI/ML accelerators have an insatiable need for more bandwidth. Processing AI/ML training models is all about speed, and the faster accelerators can move data in and out, the more efficient and cost effective the training can be executed.

Conclusion

PCIe is everywhere in modern computing architectures, and we expect PCIe 6.1 will gain quick adoption in performance-critical applications in AI/ML, HPC, cloud computing and networking.

Rambus offers PCIe 6.1 controller IP, featuring an Integrity and Data Encryption (IDE) engine which provides state-of-the-art security for the PCIe links and the valuable data transferred over them.

What’s new about PCI Express 5 (PCIe 5)? The latest PCI Express standard, PCIe 5, represents a doubling of speed over the PCIe 4.0 specifications.

We’re talking about 32 Gigatransfers per second (GT/s) vs. 16GT/s, with an aggregate x16 link duplex bandwidth of almost 128 Gigabytes per second (GB/s).

This speed boost is needed to support a new generation of artificial intelligence (AI) and machine learning (ML) applications as well as cloud-based workloads.

Both are significantly increasing network traffic. In turn, this is accelerating the implementation of higher speed networking protocols which are seeing a doubling in speed approximately every two years.

You can find much more about PCIe 5 in the article below.

Table of contents

1. PCI Express: Frequently Asked Questions (FAQ)
2. PCIe 5 – A New Era
3. PCIe 5 vs. PCIe 4 (+Comparison table included)
4. PCIe 5: Applications and Market Adoption
5. Complete PCIe 5 Interface Solutions from Rambus
6. Conclusion

PCI Express: Frequently Asked Questions (FAQ)

Let’s answer five frequently asked questions about PCI Express and PCIe 5.

a. What is PCI Express 5?

With the preliminary specification announced in 2017, PCIe 5 is a high-speed serial computer expansion bus standard that moves data at high bandwidth between multiple components. The PCIe 5.0 specification was formally released in May of 2019.

You might be wondering why a new PCI Express standard like PCIe 5 is needed. Well, PCIe 5 offers twice the data transfer rate of its PCIe 4 predecessor, delivering 32 GT/s vs. 16 GT/s. This speed increase is critical to support new AI/ML applications and cloud-centric computing.

b. Why both GT/s and GB/s?

GT/s is a measure of raw speed – how many bits can we transfer in a second. The data rate, on the other hand, has to take into consideration the overhead for encoding the signal. Bandwidth is data rate times link width, so encoding overhead’s impact on the data rate translates directly to an impact on bandwidth.

Back in the days of PCIe 2, the encoding scheme was 8b/10b, so there was a hefty overhead penalty for encoding. With such a high overhead, it was particularly useful to have measures of transfer rate (x GT/s) and data rate (y Gbps), where “y” was only 80% of “x.”
With Gen 3 and continuing through to the present Gen 5, the PCI Express standard moved to a very efficient 128b/130b encoding scheme, so the overhead penalty is now less than 2%. As such, the link speed and the data rate are roughly the same.

For a PCI 5 x8 link, 32 GT/s raw speed translates to 31.5 GB/s bandwidth (we chose a x8 link so we could go straight from bits to bytes). And since PCIe is a duplex link, total aggregate bandwidth rounds to 63GB/s (32GT/s x 8 lanes / 8 bits-per-byte x 128/130 encoding x 2 for duplex).

c. What is a PCI Express lane?

So what’s a PCI Express lane? Well, a PCIe lane consists of four wires to support two differential signaling pairs. One pair transmits data (from A to B), while the other receives data (from B to A). Want to know the best part? Each PCIe lane is designed to function as a full-duplex transceiver which can simultaneously transfer 128-bit data packets in both directions.

d. What does PCIe x16 mean?

We’ve discussed lanes, but what do they have to do with x16? Well, the term “PCIe x16” is used to refer to a 16-lane link instantiated on a board or a card. Physical PCIe links may include 1, 2, 4, 8, 12, 16 or 32 lanes. The 32-lane link is a pretty rare beast, so in practical terms the x16 represents the top end of the PCI Express link options.

e. What is PCI Express used for?

We’ve talked a lot about PCIe 5, but what is PCI Express actually used for?

You can think of the PCIe interface as the system “backbone” that transfers data at high bandwidth between various compute nodes. What’s the bottom line? Put simply, PCIe 5 rapidly moves data between CPUs, GPUs, FPGAs, networking devices and ASIC accelerators using links with various lane widths configured to meet the bandwidth requirements for the linked devices.

PCIe 5 vs. PCIe 4

Here’s a handy by-the-numbers comparison of PCIe 5 vs. PCIe 4 with the actual aggregate (duplex) bandwidth adjusted for the encoding overhead.

PCIe 5: Applications & Market Adoption

AI/ML and Cloud Computing

No surprise, PCIe 5 is the fastest PCI Express ever. While the speed upgrade makes the applications of today run faster, what’s particularly exciting is that PCIe 5 is enabling new applications in markets such as AI/ML and cloud computing.

AI applications generate, move and process massive amounts of data at real-time speeds. An example is a smart car which can generate as much as 4TB of data per day!

But that’s not all, the size of AI/ML training models are doubling every 3-4 months. The torrent of data, and the rapid growth in training models is putting tremendous stress on every aspect of the compute architecture, with interconnections between devices and systems being of critical importance. Also critical is fast access to memory as AI/ML workloads are extremely compute intensive.

But while AI/ML is one major megatrend, there are others. Data centers are changing, with enterprise workloads moving to the cloud at a rapid pace. Those applications mean moving more data, often with real-time speed and latency.

This shift to the cloud, along with ever-more sophisticated AI/ML applications, is accelerating the adoption of higher speed networking protocols that are experiencing a doubling in speed about every two years: 100GbE ->200GbE-> 400GbE.

Now this is where PCI express 5 comes in. PCIe 5 delivers duplex link bandwidth of almost 128 GB/s in a x16 configuration. Put simply, PCI express 5 effectively addresses the demands of AI/ML and cloud computing by supporting higher speed networking protocols as well as higher speed interconnections between system devices..

Complete PCI Express 5 Digital Controller Solutions from Rambus

Rambus offers a highly configurable PCIe 5.0 digital controller.

The Rambus PCIe 5.0 Controller can be paired with 3^rd-party PHYs or those developed in house. Rambus can provide integration and verification of the entire interface subsystem.

Conclusion

In “PCI Express 5 vs. 4: What’s New?” we explain how PCI Express is the system backbone that transfers data at high bandwidth between CPUs, GPUs, FPGAs and ASIC accelerators using links of variable lane widths depending on the bandwidth needs of the linked devices.

We also detail how the latest PCI Express standard, PCIe 5, represents a doubling over PCIe 4 with a raw speed of 32GT/s vs. 16GT/s translating to total duplex bandwidth for a x16 link of ~128 GB/s vs. ~64 GB/s.

We then explored how the higher data rates of PCIe 5 are enabling system designers to support a new generation of cloud computing and AI/ML applications.

Explore more primers:
– Hardware root of trust: All you need to know
– Side-channel attacks: explained
– DDR5 vs DDR4 – All the Design Challenges & Advantages
– Compute express link: All you need to know
– MACsec Explained: From A to Z
– The Ultimate Guide to HBM2E Implementation & Selection

We wrapped up a great PCI-SIG Developers Conference (DevCon) last week which really showed off the strength and momentum of the PCI Express® community. There was great engagement with everyone who stopped by the booth, and we appreciate the time of everyone who had the chance to do so. While PCIe 5.0 just recently reached the market in the latest state-of-the-art server and client systems, the demand for more bandwidth is unrelenting. So, this DevCon was the opportunity to shine the spotlight on the generation for the next wave of computing systems: PCIe® 6.0.

PCIe 6.0 represents a real watershed event for the standard, because for the first time in its storied history, we’re moving from tried-and-true NRZ to a new signaling scheme, PAM4. With PAM4 signaling (“Pulse Amplitude Modulation with four levels”) you get 2 bits per clock cycle for 4 amplitude levels (00, 01, 10, 11) vs. PCIe 5.0, and earlier generations, which used NRZ modulation with 1 bit per clock cycle and two amplitude levels (0, 1). With PAM4, instead of talking about a clean eye, we need to talk about “three clean eyes” between the four voltage levels.

That’s exactly what we demo’ed at DevCon, with our PCIe 6.0 PHY running at 64 GT/s. In long reach and short reach implementations, we showed off Bit Error Rate (BER) performance that far exceeded the spec. With SI/PI being integral to our engineering DNA, we’ve designed our PHY with the headroom to ensure first-time right implementations for the most demanding applications.

Given PAM4’s inherently higher BER compared to NRZ, the PCIe 6.0 standard incorporates Forward Error Correction (FEC) in the controller to mitigate the higher error rate. The PCIe 6.0 FEC is kept lightweight to have minimal impact on latency (under 2ns). FECs required fixed sized packets, so away go the variable packets of PCIe 5.0 and in come FLITs with PCIe 6.0.

FLIT mode packets are organized in Flow Control Units of fixed sizes, as opposed to variable sizes of past PCIe generations. In addition to supporting FEC, FLIT mode also simplifies data management at the controller level and results in higher bandwidth efficiency, lower latency, and smaller controller footprint.

In our PCIe 6.0 Digital Controller demo we showed operation to the full PCIe 6.0 spec. including FLIT mode. We sent Transaction Layer Packets (TLP) both from Root Port to Endpoint, and Endpoint to Root Port.  This demo used Root Port and End Point instantiations of the Rambus PCIe 6.0 Controller IP implemented into two internally developed FPGA boards to accommodate the current unavailability of PCIe 6.0 Host devices.  We utilized our internally developed embedded debugger and logic analyzer, XpressAGENT, to trace and display TL Packets. In compliance with the PCIe 6.0 specification, the controller is backwards compatible to non-FLIT mode NRZ operation when interoperating with PCIe 5.0 and earlier generation devices.

Whether you need a PCIe 6.0 PHY, PCIe 6.0 Digital Controller or a full PCIe 6.0 Interface Subsystem, we’ve got you covered. You can check out all our PCIe IP offerings here and get in touch with us at rambus.com.

Like many standards in the computing world, PCIe has proliferated far beyond its original remit. Over the past two decades, it has become not just the de facto standard for computing connectivity, it has also expanded into new applications, such as IoT, automotive, government, and many more. With its most recent update to PCIe 6.0, it is poised to take data center performance to the next level.

PCIe 6.0 boosts signaling rates to 64 gigatransfers per second (GT/s), twice that of PCIe 5.0. Initial designs incorporating PCIe 6.0 will be where bandwidth demands are most intense right now: in the heart of the data center. For bandwidth-hungry, data-intensive workloads, the extra bandwidth offered by PCIe 6.0 will certainly be a game changer!

CXL, first introduced in 2019, adopted the ubiquitous PCIe standard for its physical layer protocol (CXL.io). At that time, PCIe 5.0 was the latest standard, and CXL 1.0, 1.1 and the subsequent 2.0 generation all used PCIe 5.0’s 32 GT/s signaling.

In August 2022, CXL 3.0 was released, adopting the PCIe 6.0 physical interface. This new version of the CXL specification introduced new features such that promise to increase data center performance and scalability, while reducing the total cost of ownership (TCO). CXL 3.0, like PCIe 6.0, uses PAM4 to boost signaling rates to 64 GT/s with no additional latency.

Beyond this, it offers multi-tiered switching and switch-based fabrics, along with improved memory sharing and pooling capabilities. Combined, these three key features enable new use models and increased flexibility in data center architectures. This facilitates the move to distributed, composable architectures and higher performance levels for AI/ML and other compute-intensive or memory-intensive workloads.

For SoC designers, the number of signal integrity and power integrity (SI/PI) issues compound as data rates rise. Designing for 64 GT/s operation can be exceedingly tricky. Rambus has over 30 years of renowned leadership in SI/PI and has helped chip makers successfully implement hundreds of PCIe and CXL designs. With today’s announcement of a PHY that supports both PCIe 6.0 and CXL 3.0, we offer an easy to integrate solution that will help you take your chip design to the next level of performance.

At the most recent PCI-SIG® Compliance Workshop held in Burlingame, CA, Rambus achieved PCIe 5.0 compliance for two products:

• PCIe 5.0 Controller IP, which is fully backward compatible to PCIe 4.0 and PCIe 3.1/3.0. It was certified at PCIe 5.0 x4 operating at 32 GT/s as an Endpoint controller on an Xilinx® Virtex® Ultrascale+ FPGA.
• Inspector (4854) for PCIe 5.0, an interposer card for diagnostic testing, exercising and debug of PCIe devices providing PCIe 4.0 x8 16 GT/s to PCIe 5.0 x4 32 GT/s with diagnostic IP. The platform includes a PCIe 5.0 x4 Host and PCIe 5.0 capable soft switch IP.

Both products are now included on the PCI-SIG Integrators List. This list includes all products that have successfully completed the rigorous testing procedures of the Compliance Workshop.

Why is PCI-SIG compliance so important?

PCI-SIG is the organization responsible for developing and maintaining the standardized approach to peripheral component I/O data transfers. Their Compliance Workshops offer members the opportunity to test and validate their products before they enter the field. Testing is completed against PCI-SIG maintained systems, as well as other leading manufacturers of PCI Express products. Achieving Compliance Certification during these workshops provides assurance to Rambus customers that the PCIe 5.0 IP and Inspector for PCIe 5.0 fully meet the rigorous PCIe 5.0 requirements.

Is PCIe 5.0 compliance a major milestone?

Yes, while there are 800 member companies in the PCI-SIG, at the time of this writing, there are only 44 entries in the PCI-SIG Integrators List of products which have achieved PCIe 5.0 compliance. Rambus is dedicated to providing advanced PCI-SIG compliant solutions that will power chips and systems for the most challenging computing workloads.

Can you give us some facts and figures from the PCI-SIG Compliance Workshop?

Absolutely! The Compliance Workshop by the numbers:

• 4 full days of testing
• 4 nights of bug fixing
• Rambus team: 4 members (2 per product)
• 34 rooms on floors 5 and 6 of the Embassy Suite in Burlingame
• More than 40,000 steps walked on those two floors
• 29 Interops
• 1 PTC and 1 PCIe CV test for the Rambus PCIe 5.0 Controller (protocol and register testing)
• 2 LMR tests (4 hours) for the Inspector
• 10+ hours spent on LEQ tests
  • 6 Tx Eq (Eye Diagram) testing for 8 GT/s, 16 GT/s and 32 GT/s on upstream and downstream ports
  • 6 Rx Eq (Receiver quality) testing for 8 GT/s, 16 GT/s and 32 GT/s on Upstream and downstream ports
• 5 hours spent on Tx PLL 8/16/32 GT/s testing

 For more information on the Rambus PCIe 5.0 Controller and Inspector platforms, visit Rambus PCIe 5.0 Controller and Rambus PCIe Debug and Test Solutions or contact us here.